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A deep trench power MOS device structure and its preparation method

A MOS device, deep trench technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as low withstand voltage, large device leakage current, isolation structure failure, etc., to achieve the effect of improving performance

Active Publication Date: 2019-12-17
CHINA RESOURCES MICROELECTRONICS (CHONGQING) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The sources of N-type ions include the machines of each unit process, the blanks used in the production cycle, abnormal handling during machine maintenance, the factory environment, and the feeding of raw materials; N-type free ions will be produced during the process. Causes electrical drift of the device. Especially for P-type MOS tubes, after the body region (body) ion implantation and annealing process are completed, a certain concentration of free N-type ions will form a large The weak N-type interface will easily lead to the failure of the peripheral isolation structure in the terminal area of ​​the MOS device, which will lead to a relatively large leakage current and a relatively low withstand voltage of the device, which is not expected by those skilled in the art

Method used

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  • A deep trench power MOS device structure and its preparation method
  • A deep trench power MOS device structure and its preparation method
  • A deep trench power MOS device structure and its preparation method

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Embodiment 1

[0053] like figure 1As shown, this embodiment relates to the present invention discloses a deep trench power MOS device structure, specifically, the deep trench power MOS device structure includes a P-type heavily doped substrate divided into a cell region and a terminal region above 100. The P-type lightly doped epitaxial layer 101 (such as a P-silicon layer) disposed on the P-type heavily doped substrate 100, and the N-type lightly doped epitaxial layer 101 disposed on the P-type lightly doped epitaxial layer 101 in the cell region The doped layer 102, the P-type source region layer 103 disposed on the N-type doped layer 102, the P-type lightly doped Several cell region trenches 104 in the heteroepitaxial layer 101, several termination region trenches 105 disposed in the P-type lightly doped epitaxial layer 101 of the termination region, and several terminal region trenches 105 disposed in the P-type lightly doped epitaxial layer 101 of the termination region A number of N-...

Embodiment 2

[0059] like figure 2 As shown, this embodiment relates to a method for preparing a deep trench power MOS device structure. Specifically, the method includes the following steps:

[0060] Step S1, providing a semiconductor structure with a cell region and a terminal region, the semiconductor structure includes a P-type heavily doped substrate 200 and a P-type lightly doped epitaxial layer 201 on the P-type heavily doped substrate 200 ( Such as P-silicon layer); preferably, the P-type heavily doped substrate 200 includes a P-type heavily doped substrate 200 (N++ silicon layer) with a first doping concentration and the A P-type heavily doped substrate 2002 (N+ silicon layer) with a second doping concentration on the P-type heavily doped substrate 2001, and the first doping concentration is greater than the second doping concentration, such as image 3 structure shown.

[0061] Specifically, the formation method of the semiconductor structure includes: epitaxial P+ silicon laye...

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Abstract

The invention relates to the technical field of semiconductor manufacturing and more particularly to a deep trench power MOS device structure and a method for producing the same. After body ion implantation and a annealing process, a covered P-type ion implantation process is added. A P-type lightly doped region is formed on the upper parts of N-type protection rings and the upper parts of P-type lightly doped epitaxial layers between adjacent N-type protection rings to resist N-type ion contamination in the process so that the isolation at the device periphery may maintain normal operation because of there is not a direct large leakage path, thereby improving the performance of the device.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a deep trench power MOS device structure and a preparation method thereof. Background technique [0002] With the continuous development of semiconductor technology, power MOS transistor devices have high input impedance, low loss, fast switching speed, no secondary breakdown, wide safe working area, good dynamic performance, and easy coupling with the front electrode to achieve high current, With the advantages of high conversion efficiency, gradually replacing bipolar devices has become the mainstream of power device development today. [0003] At present, during the fabrication process of conventional deep trench power MOS devices, there will be free N-type ions in the clean room. The sources of N-type ions include the machines of each unit process, the blanks used in the production cycle, abnormal handling during machine maintenance, the factory environme...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06H01L21/336
CPCH01L29/0603H01L29/66666H01L29/7827
Inventor 周秀兰蒋正洋陈逸清
Owner CHINA RESOURCES MICROELECTRONICS (CHONGQING) CO LTD