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CDMA routing node based on parallel structure CODEC

A routing and node technology, applied in digital transmission systems, electrical components, transmission systems, etc., can solve the problems of large data transmission delay, high CODEC power consumption, and high complexity, reducing transmission delay, reducing hardware overhead, The effect of reducing complexity

Active Publication Date: 2017-04-26
UNIV OF ELECTRONIC SCI & TECH OF CHINA
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  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The decoding part requires an accumulator module with high complexity, etc. These factors lead to high power consumption of the CODEC
[0005] (2) The scalability of routing nodes is poor: due to the large delay of data transmission in CODEC, based on the above-mentioned CODEC routing nodes, the delay required for data jumping at each routing node is also relatively large. The current CDMA NoC generally adopts Star, Ring and extended topologies based on the number of hops between resource nodes, but these topological structures do not have good scalability, that is, the scalability of CDMA routing nodes is poor.

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  • CDMA routing node based on parallel structure CODEC
  • CDMA routing node based on parallel structure CODEC
  • CDMA routing node based on parallel structure CODEC

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Embodiment Construction

[0033] The principles and features of the present invention will be described below with reference to the accompanying drawings. The examples cited are only used to explain the present invention, and are not used to limit the scope of the present invention.

[0034] The present invention provides a CDMA on-chip network routing node based on a parallel structure CODEC, which aims to solve the problems of high data jump delay, large power consumption area and poor scalability in traditional CDMA on-chip network routing nodes.

[0035] Such as figure 1 As shown, the routing node includes a Port module, an RC (Route-Compute) module, a VA (Virtual-Channel-Allocation) module, an SA (Switch-Allocation) module, and a parallel-structured CODEC module. The Port module stores the data packet and transmits the header information (Head_Flit) to the RC module. Each FIFO buffer (First-In-First-Out) in the Port module corresponds to each input port of the upper-level routing node. E.g figure 1 For...

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Abstract

The invention relates to a CDMA routing node based on a parallel structure CODEC, and solves the problems of high data jump time delay, large power consumption area and poor expansibility in a conventional CDMA network-on-chip routing node. The CDMA routing node comprises a Port module, RC module, a VA module, an SA module and a parallel structure CODEC module. The Port module is used for storing data packets and forwarding the data packets to an MUX data selector, and transmitting packet head information to the RC module; the RC module finishes routing computation according to the packet head information of the data packets in FIFO buffers, and outputs a transmission request to the VA module; the VA module finishes allocation of lower-level storage space according to the transmission request and current resource conditions, and transmits an allocation signal to the SA module; the SA module carries out assignment on code words in the parallel structure CODEC according to the output of the VA module, selects data in the FIFO buffers through the MUX data selector, and transmits the data to the parallel structure CODEC module; and the parallel structure CODEC module outputs the selected data. The CDMA routing node reduces design complexity, reduces area and power consumption and can improve network performance in any topological-structure network.

Description

Technical field [0001] The invention relates to the field of on-chip networks, in particular to the optimization design of routing nodes in large-scale on-chip networks, and the application in engineering practice. Background technique [0002] In recent years, with the increasing complexity of the system-on-chip, the interconnection structure based on NoC (Network on Chip), due to its ability to maintain good communication performance in the complex system-on-chip, has gradually become the interconnection structure of the system-on-chip. Research hotspots. Today, NoC technology has been widely used in multi-processor system-on-chips. However, when multiple users request the same channel at the same time, data exchange is extremely prone to congestion, resulting in a rapid decline in NoC communication performance. [0003] In order to solve the above problems, researchers introduced CDMA (Code Division Multiple Access) technology into the on-chip network, but the existing serial ...

Claims

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Application Information

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IPC IPC(8): H04L12/741H04L12/747H04L12/721H04L12/801H04L45/74
CPCH04L45/14H04L45/74H04L45/742H04L47/12
Inventor 陈哲吕骏华王坚李桓李玉柏
Owner UNIV OF ELECTRONIC SCI & TECH OF CHINA
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