CDMA routing node based on parallel structure CODEC
A routing and node technology, applied in digital transmission systems, electrical components, transmission systems, etc., can solve the problems of large data transmission delay, high CODEC power consumption, and high complexity, reducing transmission delay, reducing hardware overhead, The effect of reducing complexity
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[0033] The principles and features of the present invention will be described below with reference to the accompanying drawings. The examples cited are only used to explain the present invention, and are not used to limit the scope of the present invention.
[0034] The present invention provides a CDMA on-chip network routing node based on a parallel structure CODEC, which aims to solve the problems of high data jump delay, large power consumption area and poor scalability in traditional CDMA on-chip network routing nodes.
[0035] Such as figure 1 As shown, the routing node includes a Port module, an RC (Route-Compute) module, a VA (Virtual-Channel-Allocation) module, an SA (Switch-Allocation) module, and a parallel-structured CODEC module. The Port module stores the data packet and transmits the header information (Head_Flit) to the RC module. Each FIFO buffer (First-In-First-Out) in the Port module corresponds to each input port of the upper-level routing node. E.g figure 1 For...
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