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Formation method of semiconductor structure

A semiconductor and gate structure technology, applied in the field of semiconductor structure formation, can solve the problems that the electrical properties of semiconductor structures need to be improved

Active Publication Date: 2020-04-07
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] Although the introduction of high-k metal gates can improve the electrical properties of semiconductor structures to a certain extent, the electrical properties of semiconductor structures formed by existing technologies still need to be improved.

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  • Formation method of semiconductor structure

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Embodiment Construction

[0031] As mentioned in the background art, the electrical performance of the semiconductor structure formed in the prior art needs to be improved.

[0032] It has been found through research that although the use of a high-k gate dielectric material as the material of the gate dielectric layer can improve the electrical performance of the semiconductor structure to a certain extent, for example, the leakage current (leakage current) in the semiconductor structure is reduced, however, in the semiconductor structure The relaxation current (DR Current, Dielectric Relaxation Current) is still large, resulting in poor electrical properties of the semiconductor structure, for example, the positive bias-temperature instability characteristics of the semiconductor structure (PBTI, PositiveBiase Temperature Instability) and negative bias-temperature Instability (NBTI, Negative BiaseTemperature Instability) is remarkable. Further studies have found that the reasons for the large relaxat...

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Abstract

A forming method of a semiconductor structure includes the following steps: providing a substrate; forming a high k gate medium layer on the surface of the substrate; forming a sacrificial layer on the surface of the high k gate medium layer; conducting defect passivation annealing on the high k gate medium layer, wherein the defect passivation annealing is carried out in an atmosphere lacking defect passivation ions, and the defect passivation ions enter the high k gate medium layer via the sacrificial layer during the defect passivation annealing process; removing the sacrificial layer; and forming a gate electrode layer on the surface of the high k gate medium layer. According to the method, a problem of dielectric relaxation of the high k gate medium layer is overcome, the density of the high k gate medium layer and the density of an interfacial layer are increased, and thus the electrical performance of a semiconductor structure formed by the method is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] The main semiconductor device of an integrated circuit, especially a very large scale integrated circuit, is a metal-oxide-semiconductor field effect transistor (MOS transistor). With the continuous development of integrated circuit manufacturing technology, the technology nodes of semiconductor devices are continuously reduced, and the geometric dimensions of semiconductor structures are continuously reduced following Moore's law. When the size of the semiconductor structure is reduced to a certain extent, various secondary effects caused by the physical limit of the semiconductor structure appear one after another, and it becomes more and more difficult to scale down the feature size of the semiconductor structure. Among them, in the field of semiconductor manufacturing, the most ...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/28H01L29/40
CPCH01L21/28008H01L29/408H01L29/42364H01L29/66477
Inventor 李勇
Owner SEMICON MFG INT (SHANGHAI) CORP