High-linearity low-noise amplifier for Ku waveband phase array radar

Abstract

The invention provides a high-linearity low-noise amplifier for Ku waveband phase array radar. The high-linearity low-noise amplifier comprises a first level circuit and a second level circuit, wherein the first level circuit has an emitter degeneracy inductance type cascode structure; the emitter length LE of a tube Q1 is selected for guaranteeing that the optimal signal resistance is equal to a signal resistance; under the condition of confirmed sizes of tubes Jc and Q1 (fT confirmed), the appropriate Ls and Lb are selected for realizing the matching of noise and power; the second level circuit has a cascode structure; in order to acquire higher output power, the emitter sizes of Q3 and Q4 are selected as 4 times of the sizes of Q1 and Q2; L2, L3, C3 and R1 are used for realizing the broadband output matching. According to the invention, the circuit area and the manufacturing cost are not obviously increased, and meanwhile, the linear output power is increased and the dynamic range of the circuit can be effectively improved.

Description

technical field [0001] The invention belongs to the field of electronic amplifiers, in particular to a high-linearity low-noise amplifier for a Ku-band phased array radar. Background technique [0002] Ku-band phased-array radar has high operating frequency and small overall size, and is widely used in airborne detection radars with strict space requirements and high precision requirements. As a key module of the phased array radar receiving / transmitting (T / R) unit, the low noise amplifier has an important influence on the overall performance of the system. Traditional LNAs are usually manufactured using III-V compound semiconductor processes such as GaAs and InP. This process has excellent performance in terms of noise and power handling, but high cost and low integration. In recent years, with the SiGe BiCMOS process cut-off frequency (f Ｔ ), the performance of the SiGe BiCMOS process in terms of noise and gain has reached the level of the III-V semiconductor process, a...

AI Technical Summary

Problems solved by technology

This process has excellent performance in terms of noise and power handling, but high cost and low integration

In recent years, with the SiGe BiCMOS process cut-off frequency (f Ｔ ), the performance of the SiGe BiCMOS process in terms of noise and gain has reached the level of the III-V semiconductor process, and the cost is low and the integration level is high. However, the main limitation of the SiGeBiCMOS process is the breakdown voltage and linearity. low, it is difficult to achieve high linear output power

[0003] Thrivikraman et al. carried out large-signal load-pull at the output of the second stage, and adopted a hybrid structure of high breakdown tubes and high-performance tubes in series to increase the power supply voltage. The output 1-dB compression point reached 18.5dBm, but its high-shooting through the pipe f Ｔ lower, at operating frequencies close to f Ｔ When the gain drops sharply, and the load pull is load-line matching instead of conjugate matching, resulting in the output reflection coefficient (S ２２ ) less than -10dB, poor matching

There is also a degenerate inductance introduced into the emitter of the second-stage amplifier tube (Kalyoncu et al., 2012), and the bias voltage is increased, the output 1-dB compression point can reach 16dBm, but the emitter inductance reduces the gain, and a larger Excessive power dissipation due to bias voltage

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