A kind of high voltage vdmos structure and preparation method thereof

Abstract

A high-voltage VDMOS structure and a preparation method thereof, the invention belongs to the technical field of power semiconductor devices, in order to alleviate the contradictory relationship between withstand voltage and specific on-resistance in high-voltage VDMOS devices, the invention provides a technical solution as follows: A high voltage VDMOS structure, the VDMOS structure includes a drain electrode, a gate electrode and a source electrode, an N-type heavily doped substrate is arranged above the drain electrode, in addition, the VDMOS The structure also includes an N-type drift region, a deep and wide trench, a first layer of dielectric, a second layer of dielectric, a metal layer, a P-type body region, a P-type heavily doped region, an N-type heavily doped source region, and a gate oxide layer. , gate electrode and interlayer dielectric, the beneficial effects of the present invention are: firstly, the technical solution provided by the present invention has simple process and low cost; secondly, the VDMOS structure provided by the present invention can be used in the design and manufacture of high-voltage devices.

Description

Technical field [0001] The present invention belongs to the technical field of power semiconductor devices, particularly to a high voltage power VDMOS device and a method of preparing trenches having aspect buried layer and the field plate. Background technique [0002] Power VDMOS device (e.g. figure 1 Shown) is an electronic switch which is controlled by a gate voltage switching state, when being turned on by a single carrier (electron or hole) conductivity, it has a simple control and fast switching characteristics, which is widely used power electronic system, including a switching power supply, motor drives and the like. Breakdown voltage (BV), and specific on-resistance (R on，sp The two main parameters) of the power VDMOS, wherein R on，sp With BV 2.5 Proportional with the increase of the breakdown voltage, which increases dramatically specific on-resistance, breakdown voltage for more than 200V VDMOS devices, the situation is particularly evident. [0003] There are two typ...

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Problems solved by technology

[0006] The first is the multiple epitaxy method, which requires multiple photolithography, doping and epitaxy, and the process flow is complex and costly;

[0007] The second is the deep trench epitaxial filling method. This method requires the use of an epitaxial process to fill trenches with a large aspect ratio. decrease, leakage increases;

[0008] The third method is the groove wall doping method, which uses ion implantation or diffusion to directly dope the groove wall of the trench, but it is difficult to accurately control the dopant dose and impurity distribution in this method, resulting in a decrease in the withstand voltage of the device

However, the isolated gate MOSFET structure is generally limited to low-voltage (less than 200V) devices. In order to achieve a higher withstand voltage, the trench (302) needs to have a deep and wide shape, and the bottom of the trench (302) must be There is a thick oxide layer (for example, for a device with a 600V withstand voltage level, the thickness of the oxide layer is greater than 5 μm), which poses a huge challenge to device fabrication. In addition, the use of polysilicon to fill deep and wide trenches is expensive

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