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Silicon carbide VDMOS device

A technology of silicon carbide and devices, which is applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems of reduced forward current capability of devices, lower peak electric field of gate oxide layer, etc., to reduce electric field peak value, improve electric field uniformity, increase reliability effect

Inactive Publication Date: 2017-10-27
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Shortening the width of the JFET region can reduce the peak electric field of the gate oxide layer, but it will reduce the forward current capability of the device

Method used

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  • Silicon carbide VDMOS device
  • Silicon carbide VDMOS device
  • Silicon carbide VDMOS device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0017] Such as figure 1 As shown, this example is the case where the P-type implantation region 9 is any P-type implantation, including the N+ substrate 1, the N-type epitaxial layer, and the gate structure. Wherein, the N epitaxial layer is located on the N+ substrate 1 , and the gate structure is located on the N epitaxial layer.

[0018] The gate structure covers the surface except the source, and the gate structure includes a gate dielectric layer 7 and polysilicon 8 thereon, and the polysilicon surface leads out to the gate; the upper part of the N epitaxial layer forms horizontal and vertical segmented P-type well regions 3, a JFET region 4 is formed between the P-type well regions 3, an independent N+ source region 5 and a P+ body contact region 6 are formed on the upper part of the P-type well region, wherein the N+ source region 5 surrounds the P+ body contact region 6, The common terminal of the N+ source region 5 and the P+ body contact region 6 is the source; the ...

Embodiment 2

[0023] Such as figure 2 As shown, the structure of this example is basically the same as that of Example 1, except that the P-type implanted region 9 and the P+ body contact region 6 have the same junction depth and doping concentration.

[0024] Compared with Example 1, this example can save a mask in the process, reduce one ion implantation, and reduce the cost.

Embodiment 3

[0026] Such as Figure 5 As shown, the structure of this example is basically the same as that of Example 1, except that the P-type implant region 9 and the P-type well region 3 have the same junction depth and doping concentration.

[0027] Compared with Example 1, this example can save a mask in the process, reduce one ion implantation, and reduce the cost. Compared with Example 2, the junction depth of the P-type implanted region 9 in this example is deeper, which can more significantly reduce the peak value of the electric field of the gate oxide layer and improve the withstand voltage of the device.

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Abstract

The present invention belongs to the power semiconductor technology and relates to a silicon carbide VDMOS device. The device uses a square primitive cell structure. Compared with the traditional square primitive cells, the structure is characterized by the common JFET region cross center of the four nearest primitive cells is provided with a P-type injection region. The P-type injection region can effectively absorb the power line from the drain terminal to ease concentration of the gate oxide field at the JFET region cross center under the blocking state of the device, thereby increasing the device withstand voltage and improving the gate oxide reliability of the device.

Description

technical field [0001] The invention belongs to the technical field of power semiconductors and relates to a silicon carbide VDMOS device. Background technique [0002] As the third-generation wide-bandgap semiconductor material, SiC has the characteristics of wide bandgap, high critical breakdown electric field and high thermal conductivity. It has advantages in fields such as irradiation. Since SiC has a high critical breakdown electric field, and SiO 2 The dielectric constant is lower than that of SiC, which causes the gate oxide layer of SiC VDMOS to withstand a high electric field when the device withstands voltage. For SiC VDMOS with square cells, the electric field of the gate oxide layer will The JFET area is concentrated, so the reliability problem of its gate oxide is more serious. Shortening the width of the JFET region can reduce the peak electric field of the gate oxide layer, but it will reduce the forward current capability of the device. Contents of the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/06H01L29/78
CPCH01L29/0623H01L29/7811
Inventor 罗小蓉何清源张凯方健杨霏
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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