Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

High-density embedded line making method

A production method and embedded technology, applied in printed circuit manufacturing, printed circuit, photolithography/patterning, etc., can solve problems such as fineness and stability, deformation, etc.

Active Publication Date: 2018-03-27
GUANGDONG UNIV OF TECH
View PDF4 Cites 8 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The defect of this technology is that there will still be deformation after the UV curing chemical adhesive is cured, which has a great influence on the fineness and stability of the circuit after forming.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • High-density embedded line making method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0041] (1) Structural motherboard

[0042] (1a) Clean the surface of the stainless steel plate with deionized water in an ultrasonic cleaner for 5 minutes, and then put it into a vacuum drying oven for drying treatment.

[0043] (1b) Input the pre-designed circuit pattern into the laser equipment, and cut the circuit pattern on the surface of the stainless steel plate by laser cutting. The line width and line spacing of the circuit pattern are both 2 μm, and the depth is 5 μm.

[0044] (1c) Perform surface plasma cleaning on the cut stainless steel plate for 8 minutes.

[0045] (2) Copper plating

[0046] The stainless steel plate with the circuit pattern cut out is connected to the negative circuit, and copper plating is performed on the groove of the circuit pattern. The copper layer generated during the copper plating process fills the groove of the circuit pattern, thereby obtaining the copper layer of the circuit. In this embodiment, the deposition rate of the copper la...

Embodiment 2

[0054] (1) Structural motherboard

[0055] (1a) Clean the surface of the stainless steel plate with deionized water in an ultrasonic cleaner for 5 minutes, and then put it into a vacuum drying oven for drying treatment.

[0056] (1b) Input the pre-designed circuit pattern into the electron beam equipment, and cut the circuit pattern on the surface of the stainless steel plate by electron beam cutting. The line width of the circuit pattern is 1 μm, the line spacing is 2 μm, and the depth is 6 μm.

[0057] (1c) Perform surface plasma cleaning on the cut stainless steel plate for 10 min.

[0058] (2) Copper plating

[0059] The stainless steel plate with the circuit pattern cut out is connected to the negative circuit, and copper plating is performed on the groove of the circuit pattern. The copper layer generated during the copper plating process fills the groove of the circuit pattern, thereby obtaining the copper layer of the circuit. In this embodiment, the deposition rate ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
Line widthaaaaaaaaaa
Thicknessaaaaaaaaaa
Thicknessaaaaaaaaaa
Login to View More

Abstract

The invention provides a high-density embedded line making method. The method comprises the following steps: a) a stainless steel plate is subjected to micro-nano machining to obtain a motherboard with the surface provided with a sunken preset line pattern; b) copper plating is carried out in the line pattern groove of the motherboard to obtain a copper-layer line; c) a panel whose surface is bonded with a temporary bonding adhesive is used to take the copper-layer line out, hot pressing on a substrate bonded with a bonding adhesive is carried out, and after curing, the temporary bonding adhesive is removed; and d) a chemical etching method is adopted to thin the copper layer to obtain a high-density embedded line. The embedded line made by the method can have higher stability and small linewidth and line distance, and the line integration density can be improved obviously. By adopting the technical scheme of the invention, the linewidth can reach 1 to 100 mum, and the line distance can reach 1 to 200 mum.

Description

technical field [0001] The invention relates to the technical field of packaging circuit boards, in particular to a method for manufacturing high-density embedded circuits. Background technique [0002] At present, electronic products are developing in the direction of thinner, lighter and more multifunctional. The size of integrated circuits is getting smaller and stronger, and the number of pins is increasing. This has a great impact on the integration density, precision, conductivity and stability of circuits. put forward higher requirements. [0003] At present, the mainstream process of high-density packaging circuit boards is the semi-additive method, which mainly uses copper-clad substrates or surface chemically copper-plated substrates to make circuit boards, and uses dry film to transfer circuit patterns to the substrate to produce fine circuits. Copper layer removal on non-line parts. The disadvantage of this technology is that it needs to use the dry film to exp...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H05K3/10
CPCH05K3/103H05K2203/0528
Inventor 崔成强张昱赖韬杨斌
Owner GUANGDONG UNIV OF TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com