Capacitor array structure, semiconductor memory and manufacturing method

Abstract

The invention provides a capacitor array structure, a semiconductor memory and a manufacturing method. The method is characterized by providing a semiconductor substrate and forming a sacrificial layer and a support layer on the semiconductor substrate; forming a graphical mask layer possessing a window and forming capacitance holes in the sacrificial layer and the support layer; forming lower electrode layers on bottoms and side walls of the capacitance holes and removing the sacrificial layer; forming capacitive dielectric layers on inner surfaces and outer surfaces of the lower electrode layers and forming upper electrode lining layers on surfaces of the capacitive dielectric layers; and forming upper electrode hole filling bodies on surfaces of the upper electrode lining layers, and forming upper electrode covering layers on surfaces of the upper electrode hole filling bodies. Through the above scheme, a manufacturing order of a metal contact layer and a lead layer is changed, a problem of generating sealing in advance during material layer filling is solved, filling of the upper electrode hole filling bodies is improved, electric connection performance is increased, a cushionchamber is formed, a strain in a structure material layer is released, and a problem of capacitor deformation because of thermal expansion extrusion and the like during a technology process is avoided.

Description

technical field [0001] The invention belongs to the field of semiconductor devices and manufacturing, in particular to a capacitor array structure and a manufacturing method thereof. Background technique [0002] Dynamic Random Access Memory (DRAM for short) is a semiconductor storage device commonly used in computers, and is composed of many repeated storage units. Each memory cell usually includes a capacitor and a transistor; the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor; the voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage. At present, in the DRAM process below 20nm, the DRAM adopts a stacked capacitor structure, and its capacitor (Capacitor) is a vertical cylinder with a high a...

AI Technical Summary

Problems solved by technology

[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a capacitor structure array, a semiconductor memory structure and their respective preparation methods to solve the problem of sealing and the connection between the capacitor and the metal when the filling material layer is filled in the prior art. Problems such as poor performance and capacitor deformation due to thermal expansion

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