A method of manufacturing a semiconductor device

Abstract

The invention provides a manufacture method of a semiconductor device and relates to the field of semiconductor technology. The method includes provides a semiconductor substrate on which a target material layer is formed; forming a plurality of first gap walls arranged at intervals on the target material layer; performing first plasma processing so as to modify the first gap walls and thus to form the modified first gap walls; forming a second gap wall material layer for covering the modified first gap walls and a part of the surface of the target material layer; performing second plasma processing for modifying a part of the second gap wall material layer on the top face of the modified first gap walls and a part of the second gap wall material layer on the surface of the target materiallayer so as to form a modified second gap wall material layer; removing the modified first gap walls and the modified second gap wall material layer so as to form a plurality of second gap walls arranged at intervals. The manufacture method provided by the invention improves yield an performance of the device.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a semiconductor device. Background technique [0002] With the increasing demand for high-capacity semiconductor storage devices, the integration density of semiconductor storage devices has attracted people's attention. In order to increase the integration density of semiconductor storage devices, many different methods have been adopted in the prior art. -Patterning, DP) is being widely accepted and applied as a solution in the fabrication of semiconductor devices. [0003] Double-patterning (DP) technology overcomes the K1 limitation through pitch fragmentation, and thus is widely used in the preparation of semiconductor devices. At present, in Double-Patterning (DP) technology, there are self-aligned double patterning (Self-aligned double patterning, SADP), lithography-etching-lithography-etch (Litho-Etch-Litho-Etch, LELE) And freeze coatin...

AI Technical Summary

Problems solved by technology

The traditional quadruple pattern lithography technology also has its deficiencies, for example, it is necessary to introduce complex film layer stacks to realize the pattern transfer, which forms a spacer on the mandrel in the upper layer, and defines the mandrel in the lower layer with the spacer (mandrel), and in this process, it is necessary to ensure that the mandrel formed on the lower layer is a square pattern (square pattern)

It can be seen that the traditional process has complex processes, requires multiple depositions of film layers, high process costs, and poor surface roughness of the formed spacers.

In addition, when removing the mandrel by etching, it is easy to over-etch the oxide hard mask layer on both sides of the spacer, so that the height of the oxide on both sides of each spacer is inconsistent, resulting in subsequent etching using the spacer as a mask. When the target pattern is formed on the semiconductor substrate, the formed target pattern is distorted, the pitch deviates, and the pattern transfer quality is poor, which negatively affects the robustness of the device

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