RC-IGBT (reverse conducting-insulated gate bipolar transistor) device and preparation method thereof
A device and semiconductor technology, applied in the field of reverse-conducting insulated gate bipolar transistor devices and their preparation, can solve the problems of uneven current distribution in the drift region, poor reverse recovery capability of diodes, and increased on-state voltage drop, etc. Achieve the effect of optimizing forward conduction characteristics, improving anti-latch capability, and reducing forward conduction voltage drop
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Embodiment 1
[0057] A kind of RC-IGBT device, its cell structure is like Figure 4 As shown, it includes: an N-type silicon drift region 4, an emitter structure and a gate structure located on the upper layer of the N-type silicon drift region 4, and a collector structure located on the lower layer of the N-type silicon drift region 4; the emitter structure includes a metal emitter Pole 8, N+ silicon emitter region 9, P+ silicon contact region 10 and P-type silicon base region 11, said P-type silicon base region 11 is located on top of N-type silicon drift region 4, and said N+ silicon emitter region 9 is located on P-type silicon On both sides of the top of the base region 11, the P+ silicon contact region 10 is located between and connected to the N+ silicon emitter region 9, and the metal emitter 8 is located on the upper surface of the N+ silicon emitter region 9 and the P+ silicon contact region 10; The gate structure includes a metal gate electrode 1, polysilicon 2 and a gate dielectri...
Embodiment 2
[0061] The difference between this embodiment and Embodiment 1 lies in: the number of P-type silicon collector short-circuit regions 6 and N-type silicon carbide collector short-circuit regions 13 are different; in this embodiment, the N-type silicon carbide collector short-circuit regions 13 and The number of P-type silicon collector regions 6 is not less than two, and a plurality of N-type silicon carbide collector short-circuit regions 13 and a plurality of P-type silicon collector regions 6 are arranged at intervals, such as Figure 5 Shown.
[0062] Compared with Example 1, because the current is far away from the collector short-circuit area, the current needs to pass through a lateral resistance to reach the collector short-circuit area, and because the Si / SiC heterojunction is evenly distributed at the metal collector 7 and the interval is small, it reduces The resistance value of the lateral resistance formed by the RC-IGBT above the P-type silicon collector region 6, the...
Embodiment 3
[0064] This embodiment is different from embodiment 1 in that: the N-type silicon carbide collector short-circuit area 13 is formed by using graded doping; the graded doping in this embodiment specifically refers to the N-type silicon carbide collector short-circuit area 13 The doping concentration gradually decreases from top to bottom (that is, the doping concentration ranges from the junction surface of the N-type silicon field resistance layer 5 and the N-type silicon carbide collector short-circuit region 13 to the N-type silicon carbide collector short-circuit region 13 and the metal collection The direction of the interface of the electrode 7 gradually decreases).
[0065] Such as Figure 7 Shown is the energy band diagram of the n-Si / N-SiC heterojunction formed by the gradually doped N-type silicon carbide collector short-circuit region 13 and the N-type silicon field stop layer 5. Compared with embodiment 1, the additional electronic barrier provided by this embodiment f...
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Abstract
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