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Vertical double-diffused metal-oxide semiconductor transistor and manufacturing method

An oxide semiconductor and vertical double-diffusion technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of high capacitance resistance and poor withstand voltage performance

Active Publication Date: 2018-07-27
苏州心愿美电子商务有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] In view of this, the purpose of the present invention is to provide a vertical double-diffused metal-oxide semiconductor transistor and its manufacturing method, so as to alleviate the technical problems of poor withstand voltage performance and high capacitance resistance in the prior art

Method used

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  • Vertical double-diffused metal-oxide semiconductor transistor and manufacturing method
  • Vertical double-diffused metal-oxide semiconductor transistor and manufacturing method
  • Vertical double-diffused metal-oxide semiconductor transistor and manufacturing method

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Embodiment 1

[0046] see figure 1 and figure 2 , a cross-sectional view and a top view of a vertical double-diffused metal-oxide semiconductor transistor provided by an embodiment of the present invention. A vertical double-diffused metal-oxide semiconductor transistor provided by an embodiment of the present invention includes: an N-type substrate, an N+ region 1, a P-body region 5, a PN alternating superjunction region, an N+ source region 4, and a gate oxide layer 7. Polysilicon gate 6 , dielectric layer isolation 8 , device source metal 9 and device drain metal 10 . Wherein, the N+ region is an electron drift region composed of a central region, a bottom region and a side region. The cross-section of the side area is "mouth", the cross-section of the central area is "one", located in the center of the side area, and the bottom area is square, located at the bottom of the device. The bottom region of the N+ region is a highly doped epitaxial layer, and the side region is a vertical N...

Embodiment 2

[0061] see image 3 , a flowchart of a method for fabricating a vertical double-diffused metal-oxide semiconductor transistor provided by an embodiment of the present invention. A method for fabricating a vertical double-diffused metal-oxide semiconductor transistor provided in an embodiment of the present invention includes:

[0062] Step S1: Provide an N-type substrate (not shown in the figure), form an N+ epitaxial layer on the upper surface of the N-type substrate, and form multiple layers of alternately arranged P+ layers and N+ layers laterally spaced on the upper surface of the N+ epitaxial layer epitaxial layer, and the upper and lower surfaces of the multi-layer epitaxial layer are both P+ layers. see Figure 4 , the product schematic diagram of step S1 in the method for fabricating a vertical double-diffused metal-oxide semiconductor transistor provided in an embodiment of the present invention.

[0063] Step S2: A trench is formed in the center of the multi-layer...

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Abstract

The invention provides a vertical double-diffused metal-oxide semiconductor transistor and a manufacturing method, within the technical field of semiconductor chips. The transistor comprises: a N-typesubstrate, a N+ region, a P body region, a PN alternating super junction region, a N+ source region, a gate oxide layer, a polysilicon gate, a dielectric layer isolation, a device source metal and device drain metal; the oxide layer covers the upper surface of the junction of the N+ source region, the N+ region, and the P body region. A polysilicon gate is disposed above the gate oxide layer. Thegate oxide layer and the polysilicon gate are 'convex' type layers, wherein an upper surface of a central region of the N+ region is higher than an upper surface of the P body region. The upper surface of the side region of the N+ region is higher than the upper surface of the PN alternating super junction region; the PN alternating super junction region is alternately arranged by the P+ layer and the N+ layer. The technical solution alleviates the technical problems of poor pressure resistance and high capacitance resistance of the prior art, improves the withstand voltage capability of thedevice and the saturation current, and greatly reduces the gate oxide capacitance of the device.

Description

technical field [0001] The invention relates to the technical field of semiconductor chips, in particular to a vertical double-diffused metal-oxide semiconductor transistor and a manufacturing method thereof. Background technique [0002] Vertical double-diffused metal-oxide semiconductor transistors have the advantages of both bipolar transistors and ordinary MOS devices. Regardless of switching applications or linear applications, VDMOS is an ideal power device. VDMOS is mainly used in motor speed regulation, inverter, uninterruptible power supply, electronic switch, hi-fi audio, automotive electrical appliances and electronic ballast, etc. VDMOS is divided into enhanced VDMOS and depletion VDMOS. With the development of the field of semiconductor design and semiconductor technology, the current VDMOS devices have been developing towards low-cost and high-performance fields. Higher performance and lower cost mean wider market applications. In the process of realizing the...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L21/336H01L29/78
CPCH01L29/0657H01L29/66712H01L29/7802
Inventor 丛艳欣李亚娜王海韵储团结
Owner 苏州心愿美电子商务有限公司