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HJT battery passivation process

A process and battery technology, applied in the field of new energy photovoltaic crystalline silicon cells

Pending Publication Date: 2018-09-14
晋能光伏技术有限责任公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since the i-layer on the p-side has a significant impact on the performance of the battery, the key to improving the performance of HJT batteries is to passivate the i-layer on the p-side and match the energy band between the i-layer and the p-layer. The essence is to adjust the amorphous silicon film through process optimization. There is no good solution in the prior art for the hydrogen content and the bonding method of hydrogen

Method used

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  • HJT battery passivation process

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Effect test

Embodiment 1

[0019] As shown in the figure, the HJT battery passivation process of this embodiment includes the following steps:

[0020] A. First, the N-type monocrystalline silicon wafer 1 is cleaned by texturing. The specific cleaning process steps are: pre-cleaning-texturing-SC1 cleaning-CP-SC2 cleaning-DHF cleaning. After texturing and cleaning, the size of the suede surface is 3um, and the reflection The rate is 11%;

[0021] B. Using PECVD process using pure silane (SiH4) as precursor for i Film layer 2 is deposited, and the deposition rate is controlled at 3 Angstroms / s, i The thickness of the film layer is 3nm;

[0022] C. Use PECVD process to dilute silane with H2 for i Film formation, hydrogen dilution (S H =[H 2 ] / [SiH 4 +H 2 ]) is 85%, the deposition rate is controlled at 1 Å / s, i The thickness of the film layer 3 is 2nm, and then double-layer passivation is performed on the two film layers. In this process, the double-layer passivation technology is adopted. Due t...

Embodiment 2

[0027] As shown in the figure, the HJT battery passivation process of this embodiment includes the following steps:

[0028] A. First, N-type monocrystalline silicon wafer 1 is subjected to texturing cleaning. The specific cleaning process steps are: pre-cleaning - texturing - SC1 cleaning - CP - SC2 cleaning - DHF cleaning, and the suede surface after texturing cleaning The size is 5um, and the reflectivity is 12%;

[0029] B. Using PECVD process using pure silane (SiH4) as precursor for i Film layer 2 is deposited, and the deposition rate is controlled at 4 angstroms / s, i The thickness of the film layer is 4nm;

[0030] C. Use PECVD process to dilute silane with H2 for i Film formation, hydrogen dilution (S H =[H 2 ] / [SiH 4 +H 2 ]) is 90%, the deposition rate is controlled at 2 Å / s, i The thickness of the film layer 3 is 3nm, and then double-layer passivation is performed on the two film layers. In this process, the double-layer passivation technology is adopted....

Embodiment 3

[0035] As shown in the figure, the HJT battery passivation process of this embodiment includes the following steps:

[0036] A. First, N-type monocrystalline silicon wafer 1 is subjected to texturing cleaning. The specific cleaning process steps are: pre-cleaning - texturing - SC1 cleaning - CP - SC2 cleaning - DHF cleaning, and the suede surface after texturing cleaning The size is 10um, and the reflectivity is 13%;

[0037] B. Using PECVD process using pure silane (SiH4) as precursor for i Film layer 2 is deposited, and the deposition rate is controlled at 5 angstroms / s, i The thickness of the film layer is 5nm;

[0038] C. Use PECVD process to dilute silane with H2 for i Film formation, hydrogen dilution (S H =[H 2 ] / [SiH 4 +H 2 ]) is 95%, the deposition rate is controlled at 3 Angstroms / s, i The thickness of the film layer 3 is 4nm, and then double-layer passivation is performed on the two film layers. In this process, the double-layer passivation technology is...

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Abstract

The present invention discloses an HJT battery passivation process. The process comprises the following steps of: A, performing texturing cleaning of an N-type monocrystalline silicon piece, wherein the size of the texturing after texturing cleaning is 3-10 [Mu]m, and the reflection of the texturing is 11-13%; B, employing a PECVD process to take pure silane as a precursor to perform iI film deposition; C, employing H2 attenuation silane to perform iII film formation, and performing dual-layer passivation of the two layers of films; D, taking the silane as the precursor, doping with diborane to prepare a p-a-Si:H film; E, employing a PVD / RPD process to deposit a TCO conductive film on the p-a-Si:H film; and F, employing the screen printing technology to perform metallization to form a metal electrode. The process method greatly optimizes the noncrystalline silicon passivation film band gap, effectively reduces the defect mode intensity of the interface and enhances the passivation effect; and moreover, the HJT battery passivation process reduces the bombard energy of the plasma to the surface especial for a RF power device so as to reduce the damaging of the surface of the siliconwafer.

Description

technical field [0001] The invention relates to a new energy photovoltaic crystalline silicon battery technology, in particular to a HJT battery passivation process. Background technique [0002] HJT cells are high-efficiency crystalline silicon solar cells that can be realized at low cost. The battery uses high-life n-type silicon as a substrate, and deposits an intrinsic amorphous silicon film and a p-type amorphous silicon film in sequence on the front side of a silicon wafer that has been cleaned by texturing, thereby forming a p-n heterojunction. Intrinsic amorphous silicon film and n-type amorphous silicon film are deposited sequentially on the back of the silicon wafer to form a back surface field. Then deposit a transparent conductive oxide film on both sides of the doped amorphous silicon film, and finally form metal electrodes on both sides by screen printing technology to form a HJT solar cell with a symmetrical structure. Low temperature, no LID and PID effects...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L31/18H01L31/0216
CPCH01L31/0216H01L31/18Y02P70/50
Inventor 张娟李高非王继磊易治凯白炎辉黄金鲍少娟高勇崔宁王广为
Owner 晋能光伏技术有限责任公司