HJT battery passivation process
A process and battery technology, applied in the field of new energy photovoltaic crystalline silicon cells
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Embodiment 1
[0019] As shown in the figure, the HJT battery passivation process of this embodiment includes the following steps:
[0020] A. First, the N-type monocrystalline silicon wafer 1 is cleaned by texturing. The specific cleaning process steps are: pre-cleaning-texturing-SC1 cleaning-CP-SC2 cleaning-DHF cleaning. After texturing and cleaning, the size of the suede surface is 3um, and the reflection The rate is 11%;
[0021] B. Using PECVD process using pure silane (SiH4) as precursor for i Film layer 2 is deposited, and the deposition rate is controlled at 3 Angstroms / s, i The thickness of the film layer is 3nm;
[0022] C. Use PECVD process to dilute silane with H2 for i Film formation, hydrogen dilution (S H =[H 2 ] / [SiH 4 +H 2 ]) is 85%, the deposition rate is controlled at 1 Å / s, i The thickness of the film layer 3 is 2nm, and then double-layer passivation is performed on the two film layers. In this process, the double-layer passivation technology is adopted. Due t...
Embodiment 2
[0027] As shown in the figure, the HJT battery passivation process of this embodiment includes the following steps:
[0028] A. First, N-type monocrystalline silicon wafer 1 is subjected to texturing cleaning. The specific cleaning process steps are: pre-cleaning - texturing - SC1 cleaning - CP - SC2 cleaning - DHF cleaning, and the suede surface after texturing cleaning The size is 5um, and the reflectivity is 12%;
[0029] B. Using PECVD process using pure silane (SiH4) as precursor for i Film layer 2 is deposited, and the deposition rate is controlled at 4 angstroms / s, i The thickness of the film layer is 4nm;
[0030] C. Use PECVD process to dilute silane with H2 for i Film formation, hydrogen dilution (S H =[H 2 ] / [SiH 4 +H 2 ]) is 90%, the deposition rate is controlled at 2 Å / s, i The thickness of the film layer 3 is 3nm, and then double-layer passivation is performed on the two film layers. In this process, the double-layer passivation technology is adopted....
Embodiment 3
[0035] As shown in the figure, the HJT battery passivation process of this embodiment includes the following steps:
[0036] A. First, N-type monocrystalline silicon wafer 1 is subjected to texturing cleaning. The specific cleaning process steps are: pre-cleaning - texturing - SC1 cleaning - CP - SC2 cleaning - DHF cleaning, and the suede surface after texturing cleaning The size is 10um, and the reflectivity is 13%;
[0037] B. Using PECVD process using pure silane (SiH4) as precursor for i Film layer 2 is deposited, and the deposition rate is controlled at 5 angstroms / s, i The thickness of the film layer is 5nm;
[0038] C. Use PECVD process to dilute silane with H2 for i Film formation, hydrogen dilution (S H =[H 2 ] / [SiH 4 +H 2 ]) is 95%, the deposition rate is controlled at 3 Angstroms / s, i The thickness of the film layer 3 is 4nm, and then double-layer passivation is performed on the two film layers. In this process, the double-layer passivation technology is...
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Abstract
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