Multi-channel-based high-speed ADC phase self-correcting method

A self-calibrating, multi-channel technology, applied in analog/digital conversion calibration/testing, code conversion, electrical components, etc., which can solve the problems of difficult to correct phase consistency, difficult to guarantee phase consistency, and non-adjustable clock phase. Achieve the effect of adjustable synchronization accuracy, low power consumption and small size

Active Publication Date: 2018-10-09
CHENGDU GUORONG TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The third is based on the second derived high real-time array scheme, using multi-channel synchronous sampling, which has the advantage of enhancing real-time performance, but the disadvantages are large volume, high power consumption, and poor synchronization accuracy.
The poor synchronization accuracy is mainly due to the addition of low-noise amplifiers, mixers and filters in the down-conversion part, so it is difficult to ensure phase consistency. At the same time, it is difficult to correct the phase consistency due to the non-adjustable clock phase.

Method used

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Embodiment 1

[0045] A method for phase self-calibration based on a multi-channel high-speed ADC, mainly comprising the following steps:

[0046] Step E1: data acquisition, each channel performs data acquisition on the analog signal, and then sends the corresponding signal to the FPGA, and the FPGA performs FFT transformation on each channel to extract the phase value of each channel;

[0047] Step E2: Select a reference channel and calculate the phase difference of each channel according to the reference channel;

[0048] Step E3: Calculate the correction value, perform self-calibration, calculate the correction value of each channel and perform correction to ensure that the difference of all channels is within 3 degrees; send the calibration command "calibration", and the FPGA starts to perform self-calibration after receiving the decoded command, To ensure that the phase difference between all boards is consistent.

[0049] Acquisition and real-time signal processing modules based on mu...

Embodiment 2

[0053] This embodiment is further optimized on the basis of Embodiment 1. The model of the ADC acquisition system is AD9208, the model of the FPGA system is XC7VX690T-2FFG1927I, the model of the DSP is TMS320C6678ACYPA, and the model of the clock system is HMC7044 .

[0054] The signal processing module of the present invention adopts a high-speed serial ADC device, has the advantages of high sampling rate, can directly collect radio frequency signals, wide bandwidth of input analog signals, small size, high real-time performance, and good synchronization accuracy; the present invention can collect radio frequency direct sampling The frequency of the signal can reach 5GHz; the sampling rate is high, up to 3Gsps; based on the array design, the real-time performance of signal processing is high; the data line of the analog-to-digital connection is small, the signal integrity is good, and the complexity of the system is reduced. Better practicality.

[0055] Other parts of this ...

Embodiment 3

[0057] This embodiment is further optimized on the basis of Embodiment 2, the clock includes DeviceCLKA, SysrefCLKA, SYNC; the DeviceCLKA is a sampling clock, and the SysrefCLKA indicates the edge of DeviceCLKA as a reference for the deterministic delay of multiple devices; The above SYNC is used to establish a data transmission path between ADC and FPGA; data exchange is performed between each board through a dedicated communication interface; for example Figure 6 As shown, after the ADC quantizes and encodes the analog signal, the parameters of the JESD204B link are configured; the ADC and the FPGA establish a data transmission path, start normal acquisition, and send the data to the FPGA, and the FPGA preprocesses the data. Send the data to the DSP through the SRIO of the X8 for further processing. If the DSP processing result needs to be sent, it will be sent to the external device or the data central station through the Gigabit Ethernet port of the DSP.

[0058] For the ...

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Abstract

The invention discloses a multi-channel-based high-speed ADC phase self-correcting method, comprising the steps of collecting data; selecting a reference channel and calculating the phase differencesof channels according to the reference channel; and calculating a corrected value and carrying out self-correcting. According to the method, the phase delay of the channels is effectively eliminated,synchronization precision is adjustable, and the practicability is excellent. The method is based on an array design, so that the instantaneity of processing signals is high; the analog-digital docking part has fewer data lines and good signal integrity and reduces the system complexity; a radio frequency preprocessing module is eliminated, so that the power consumption is low and the size is small; the number of channels of an array is configured according to different requirements, thus the use is flexible and convenient; and the sampling rate is configured according to different requirements, thus meeting different application requirements.

Description

technical field [0001] The invention belongs to the technical field of multi-channel signal processing, in particular to a multi-channel high-speed ADC phase self-calibration method. Background technique [0002] In the field of acquisition, people have higher and higher requirements for the real-time processing speed of the signal, and the bandwidth of the signal is also wider and wider. There are three conventional processing schemes: [0003] The first solution is to use a traditional ADC to collect and process signals. The advantage of this solution is low cost, but the disadvantages are low sampling rate, narrow signal bandwidth, low frequency (tens of megabytes to below 500MHz), and signal processing in unknown directions. Low real-time performance (requires antenna rotation to capture the signal). [0004] The second type is developed on the basis of the first type, that is, the down-conversion part is added before sampling. In order to take into account the two poi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/10
CPCH03M1/1023
Inventor 陈科锋
Owner CHENGDU GUORONG TECH
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