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Semiconductor structures and methods of forming them

A semiconductor and isolation structure technology, which is applied in the field of semiconductor structure and its formation, can solve the problems that the electrical properties of semiconductor structures need to be improved, and achieve the effects of reducing plasma damage by lateral etching, improving electrical properties, and improving removal effect

Active Publication Date: 2021-12-14
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the electrical performance of prior art semiconductor structures needs to be improved

Method used

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  • Semiconductor structures and methods of forming them
  • Semiconductor structures and methods of forming them
  • Semiconductor structures and methods of forming them

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0015] It can be seen from the background art that the electrical performance of the semiconductor structure in the prior art needs to be improved. Analyze the reasons for this:

[0016] In semiconductor manufacturing, with the continuous reduction of feature size, in order to effectively fill the lithography gap of smaller nodes, improve the minimum pitch between adjacent semiconductor patterns, and improve the line width roughness (Liner WidthRoughness) , LWR) and line edge roughness (Liner Edge Roughness, LER), self-alignment process is more and more widely used in fin formation process, such as self-aligned double patterned (Self-aligned Double Patterned, SADP) craft.

[0017] Among them, according to the actual layout (layout) design, the pattern density of each area of ​​the substrate is not exactly the same, and the pattern density of the substrate surface is distinguished, and the substrate includes a pattern dense area (Dense Area) and a pattern sparse area (ISO Area...

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PUM

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Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, the substrate includes adjacent device regions and isolation regions, discrete fins are formed on the substrate, and between adjacent fins The distances are equal; a protective layer is formed on the sidewall of the fin; the protective layer and the fin with a partial thickness of the isolation region are etched and removed by the first etching process; the remaining protective layer is used as a mask, and the second etching is used etching the remaining fins of the isolation region to form dummy fins; after the second etching process, removing the remaining protective layer; after removing the remaining protective layer, forming an isolation structure on the substrate , the top of the isolation structure is lower than the top of the device region fin and higher than the top of the dummy fin. The invention divides the step of etching the fin of the isolation region into two steps, thereby increasing the etching process window for removing the fin of the isolation region and reducing the etching damage to the fin of the adjacent device region.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] In the field of semiconductor manufacturing, with the development trend of VLSI, the feature size of integrated circuits continues to decrease. In order to adapt to the reduction of feature size, the channel length of MOSFET field effect transistors is also continuously shortened accordingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the control ability of the gate to the channel becomes worse, and the gate voltage pinches off the channel. The difficulty is also increasing, making the phenomenon of subthreshold leakage (subthreshold leakage), the so-called short-channel effect (SCE: short-channel effects) more likely to occur. [0003] Therefore, in order to better adapt to the reductio...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L21/336
CPCH01L29/66795H01L29/7853H01L21/31116H01L29/6681H01L21/76232H01L21/3065H01L27/0886H01L21/31111H01L21/3086
Inventor 胡华勇林益世
Owner SEMICON MFG INT (SHANGHAI) CORP
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