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An Efficient Fault Tolerant Wireless Interface in On-chip Wireless Networks

A wireless interface and wireless network technology, applied in the application field of integrated circuit chip design, can solve problems such as reducing network performance, increasing transmission delay, congestion, etc., to achieve the effect of improving data transmission efficiency, reducing transmission delay, and reducing network load

Active Publication Date: 2020-11-06
HEFEI UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The error detection strategy between nodes in the traditional NoC structure is to add an additional detection module between each pair of nodes, and can notify the source node to retransmit data when a fault is found, but this strategy has a high area overhead, and in In the case of multiple failures, a large number of retransmitted packets will be generated, which will affect the network throughput
A strategy based on inter-node detection and retransmission has been adopted. The strategy reduces the number of retransmitted data packets. Jump-to-hop detection and retransmission ensures the reliability of data transmission, but the detection and retransmission module of each port will also bring to a large area overhead
There is a fault-tolerant strategy based on NoC adaptive erasure (RAS) of the traditional mesh structure, which adopts a multi-layer error correction and detection scheme, proposes a dynamic method for fault location, and adapts fault coverage according to requirements, but this Strategies can only be applied in small-scale traditional NoCs, with high latency in larger-scale NoCs
WiNoC's error control code (Error control code, ECC) has also been proposed. By using interleaved Hamming codes in wireless links, joint crosstalk is used in wired links to avoid triple error correction and four parallel error detection codes (JTEC-SQED ), but this wireless detection and error correction method needs to wait for the transmission of the entire data packet to complete, which has high delay and buffer area overhead
There is also an improvement to the ECC scheme, using the characteristics that multiple wireless nodes can receive data at the same time, the source wireless node receives the data forwarded by the intermediate wireless node to the destination wireless node, and compares it with the data in its own retransmission buffer to judge the data transmission Whether an error has occurred, but this method is only applicable to wireless networks that require wireless multi-hop store-and-forward. For a millimeter-wave wireless network that is reachable by one hop, it takes up a lot of antenna and wireless interface area overhead, and also increases transmission. Delay
The above existing technologies all use data redundancy and path redundancy to perform data fault tolerance, and there are the following problems in common: First, it fails to take advantage of the characteristics of wireless channel broadcasting to adopt any optimal design for the confirmation information feedback of data packets in the wireless channel ; Second, with the expansion of the network scale, if the data transmitted through the wireless channel has an error near the destination node, then the request to resend the data from the source node needs to send back the fault information to the source node, and then retransmit the data. It takes a long period of time and takes up a lot of network resources. Third, wireless nodes, as important nodes of WiNoC, carry a large amount of data transmission tasks. A large amount of data retransmission caused by data errors will seriously affect the transmission efficiency of wireless nodes, and even It will cause problems such as congestion and greatly reduce network performance.

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  • An Efficient Fault Tolerant Wireless Interface in On-chip Wireless Networks
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  • An Efficient Fault Tolerant Wireless Interface in On-chip Wireless Networks

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Embodiment Construction

[0028]In this embodiment, the highly efficient fault-tolerant wireless interface in the on-chip wireless network adopts the combination transmission mode of wireless confirmation information to confirm the wireless data; the retransmission data buffer is set at the wireless interface sending end to reduce the transmission distance of the retransmission data; according to the wireless The data transmission error rate in the network is encoded with different strengths to improve the robustness of the wireless channel.

[0029] In this embodiment, the wireless interface performs data transmission as follows:

[0030] Step a. When any wireless interface A obtains a transmission token, check the reception of all wireless data in the on-chip wireless network in the previous token passing cycle, and obtain data transmission confirmation information. The time it takes for all wireless interfaces to transfer a cycle sequentially. The received wireless data refers to: in a token transfe...

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Abstract

The invention discloses a high-efficiency fault-tolerant wireless interface in an on-chip wireless network, which is characterized in that a retransmission data buffer is set at the wireless interface sending end to reduce the transmission distance of retransmission data; Data confirmation; according to the data transmission error rate in the wireless network, coding with different strengths is used to improve the robustness of the wireless channel. The present invention uses a small additional area and power consumption overhead, efficiently completes the confirmation feedback of on-chip wireless data, and can ensure lower network delay and higher saturation throughput in the network when the error rate is high , greatly improving the performance of the network.

Description

technical field [0001] The invention belongs to the application technical field of integrated circuit chip design, in particular to a wireless interface for efficiently confirming signal fault tolerance in an on-chip network. Background technique [0002] Since the 1950s, semiconductor technology has developed rapidly, and chip manufacturing technology has continued to improve. It is estimated that by 2028, the gate length of MOS transistors will be reduced from the current 16nm to 1nm. At the same time, the number of cores integrated on a chip is rapidly increasing, for example, Intel's Xeon Phi processor has been upgraded to a scale of 72 cores. The increase in the number of integrated cores on a chip puts forward higher requirements on the communication of the Network on Chip (NoC). The NoC with traditional planar metal interconnection can no longer meet the needs of on-chip communication due to problems such as high power consumption and high delay caused by many hops. ...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L1/08H04L1/00H04L12/925G06F15/78H04L47/722
CPCH04L1/0009H04L1/08H04L47/722G06F15/7825Y02D10/00
Inventor 欧阳一鸣钱昌杜高明李建华梁华国
Owner HEFEI UNIV OF TECH