Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Semiconductor device structure and fabrication method thereof

A technology of device structure and fabrication method, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., can solve the problems affecting mass production of semiconductor devices, shrinking channel length, and high manufacturing cost, and reducing short channel Channel effect, reduce the voltage required for turn-off, and improve the effect of migration

Active Publication Date: 2021-05-18
SIEN QINGDAO INTEGRATED CIRCUITS CO LTD
View PDF6 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when the channel length of the device enters the deep nanometer scale, the doping concentration of the source-drain abrupt PN junction of the traditional inversion channel device needs to change several orders of magnitude within a few nanometers. The realization of such a large concentration gradient is very important for doping technology. The design will bring great difficulties, and the manufacturing cost of these complex processes is very high, which affects the mass production of semiconductor devices
In addition, the limit size of the space charge region of the abrupt PN junction is on the order of nanometers, so the existence of the abrupt PN junction physically limits the further reduction of the channel length

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor device structure and fabrication method thereof
  • Semiconductor device structure and fabrication method thereof
  • Semiconductor device structure and fabrication method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0056] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0057] see Figure 2 to Figure 13 . It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of ​​the present invention, so that only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and th...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
Login to View More

Abstract

The invention provides a semiconductor device structure and a manufacturing method thereof. The semiconductor device structure includes: a substrate; a P-type semiconductor channel suspended above the substrate; an N-type semiconductor channel suspended above the substrate The gate dielectric layer is surrounded by the P-type semiconductor channel and the N-type semiconductor channel; the gate electrode layer is surrounded by the gate dielectric layer; the P-type source region and the P-type drain region are respectively connected to the The two ends of the P-type semiconductor channel; and the N-type source region and the N-type drain region are respectively connected to the two ends of the N-type semiconductor channel; wherein, the cross-sectional width of the P-type semiconductor channel is greater than that of the N Type semiconductor channel cross-sectional width. The invention can realize multi-layer stacking of devices in a unit area, effectively shorten the channel length of the device, reduce the short channel effect, improve the load capacity of the device, and effectively improve the integration degree of the device.

Description

technical field [0001] The invention belongs to the design and manufacture of integrated circuits, in particular to a three-dimensional stacked junctionless semiconductor device structure and a manufacturing method thereof. Background technique [0002] With the continuous development of semiconductor technology, the size of semiconductor devices is continuously reduced, the performance of driving current is continuously improved, and the power consumption is continuously reduced. production cost. [0003] Fin Field-Effect Transistor (FinFET) is a new complementary metal oxide semiconductor transistor. The shape of FinFET is similar to that of a fish fin. This design can improve circuit control and reduce leakage current, shortening the gate length of transistors. [0004] FinFET is an innovative design derived from the traditional standard transistor—Field-Effect Transistor (FET). In the traditional transistor structure, the gate can only control the on and off of the cu...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/092H01L29/06H01L29/78H01L21/8238
CPCH01L21/823807H01L27/0922H01L27/0924H01L29/0657H01L29/7854
Inventor 肖德元
Owner SIEN QINGDAO INTEGRATED CIRCUITS CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products