Semi-conductor memory device

Abstract

To provide a semiconductor memory capable of shortening the test time and performing a burn-in test in a wafer state regardless of the configuration of a memory cell array. Ring oscillator 128 is activated by external burn-in test designation signal SBT, and the row address signal output from internal row address generation circuit 122 based on the output is supplied to row decoder 102 after being scrambled by arithmetic circuit 124 . On the other hand, the signal output from the data output circuit 174 is scrambled by the data scrambler 176 according to the activation of the signal SBT, and the data of the check structure corresponding to the physical address of the memory cell array is provided to the memory cell array.

Description

technical field [0001] The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory capable of high-speed semiconductor memory testing. Background technique [0002] Accompanying the increase in storage capacity in semiconductor memories, especially dynamic RAM (hereinafter, referred to as DRAM), the time required for semiconductor memory testing has also rapidly increased. [0003] The reason for this problem is that as the storage capacity of the semiconductor memory increases, the number of word lines included in the semiconductor memory increases. Therefore, writing and reading of memory cell information is performed while the word lines are sequentially selected. The working hours become very long. [0004] The above-mentioned problems are particularly severe in burn-in tests and the like. In this burn-in test, the semiconductor memory is operated under high-temperature and high-voltage conditions, so that the performance of...

AI Technical Summary

Problems solved by technology

[0049] Second, according to the processing capability of the test device, the address scrambling processing that can be realized by software is limited

[0056] However, it is not only mechanically difficult to make such probes come into contact with each chip on the entire surface of the wafer, but also the load on the test equipment for performing such a parallel test process is too heavy.

Images