A semiconductor structure of a split-gate flash memory unit and its manufacturing method

Abstract

The invention provides a semiconductor structure of a split-gate flash memory unit and a manufacturing method thereof. The split-gate flash memory unit provided by the present invention at least includes a selection gate and a floating gate formed on a substrate, a partition wall is formed on one side of the selection gate, and the floating gate is formed on the other side of the partition wall, An ion implantation region is formed on the upper part of the substrate below the isolation wall, wherein the ion implantation type of the ion implantation region is different from the ion implantation type of the substrate. The present invention also provides a manufacturing method for manufacturing the above split-gate flash memory unit. The manufacturing method provided by the present invention can be compatible with the existing manufacturing process of the split-gate flash memory unit without increasing process cost and process complexity. The manufactured split-gate flash memory unit can reduce the influence of the channel inversion depletion region on the channel current, thereby improving the characteristics of the flash memory unit channel current and optimizing device performance.

Description

technical field [0001] The invention relates to the field of semiconductor structure and its manufacture, in particular to a structure of a split-gate flash memory unit and its manufacture. Background technique [0002] Flash memory (Flash Memory) is widely used in various fields, including consumer electronics, network communication equipment, and industrial instrumentation embedded systems, due to its non-volatile nature, easy programming, erasing, long service life, and low cost. , Automotive devices, etc. As a kind of flash memory, the split-gate flash memory based on the floating gate structure adopts the source-side channel electron injection (Source-Side Hot Electron injection) mechanism for programming operation, and uses two layers of polysilicon, the floating gate and the erasing gate, to build an electric field-enhanced type Tunneling (Poly-to-Poly Enhance Tunneling) for erasing operations has higher programming / erasing efficiency, so a thicker tunnel dielectric ...

AI Technical Summary

Problems solved by technology

For CMOS split-gate flash memory cells, the pure P-type doped region under the isolation film layer between the selection gate and the floating gate in the existing process will become a depletion region when the channel is inverted, so that the current reading When , it is equivalent to connecting a large resistor in series between the select gate channel and the floating gate channel, resulting in a low current

[0004] With the development of flash memory technology toward high integration, the size and operating voltage of flash memory cells continue to shrink, and the level of channel current continues to decrease. significantly increased impact, resulting in a shrinking flash cell erase window, which ultimately leads to an increase in the number of erase-related failures in yield and reliability testing

Images