Lossless buffer circuit for suppressing GaN half-bridge module voltage spike and current resonance and test circuit thereof
A buffer circuit, voltage spike technology, applied in electronic circuit testing, high-efficiency power electronic conversion, measurement of electricity and other directions, can solve problems such as endangering system stability, fast switching speed, etc., to avoid current oscillation, suppress voltage spikes and current resonance, The effect of promoting the stability of the system
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specific Embodiment approach 1
[0029] Specific implementation mode 1. Combination figure 1 As shown, the first aspect of the present invention provides a non-destructive snubber circuit that suppresses voltage spikes and current resonance of a GaN half-bridge module. Composed in series; the lossless snubber circuit is connected between the drain of the power device of the upper bridge arm and the source of the power device of the lower bridge arm of the GaN half-bridge module.
[0030] The non-destructive snubber circuit described in this embodiment is used in a GaN half-bridge module, which can alleviate the large turn-off voltage peak and the resonant current in the power loop caused by the fast switching process of the power device. The specific connection relationship between it and the GaN half-bridge module is as follows: figure 1 shown in .
[0031] As an example, combining figure 1 As shown, the lossless snubber circuit can adopt the following specific connection relationship: including the induc...
specific Embodiment approach 2
[0049] Specific embodiment two, combine figure 1 As shown, another aspect of the present invention also provides a test circuit for a non-destructive snubber circuit, the non-destructive snubber circuit comprising the suppressing GaN half-bridge module voltage spike and A non-destructive snubber circuit for current resonance, the test circuit includes the upper bridge arm power device Q of the GaN half bridge module 1 , Lower arm power device Q 2 , lossless snubber circuit, load inductance L, DC source VCC, power loop parasitic inductance L 1 , Power loop parasitic inductance L 2 , Power loop parasitic inductance L 3 , Power loop parasitic inductance L 4 ;
[0050] For the high-side power device Q 1 , whose gate-to-drain parasitic capacitance is C gd1 , the gate-to-source parasitic capacitance is C gs1 , the drain-source parasitic capacitance is C ds1 , the drain parasitic inductance is L d1 , the source parasitic inductance is L cs1 ;
[0051] For the lower bridge...
specific Embodiment
[0060] Specific embodiments: Taking the GaN HEMT semiconductor device GS66508B of GaN Systems Company as an example, the bus voltage of the test circuit is designed to be 400V, and the peak voltage is allowed to be 450V. According to the above calculation method, the absorbing capacitance C s1 The value is 100nF, C s2 The value is 10nF, L s The value is 0.3uH. It has been tested and verified that the non-destructive snubber circuit that suppresses the resonance of the turn-off peak voltage and current does not increase the snubber loss, and can simultaneously suppress the resonance of the peak voltage and the module outlet current.
[0061] In order to compare the effect of the present invention on suppressing voltage spikes and current resonance, this embodiment is based on the Pspice simulation model of the GS66508B chip, and a Pspice-based double-pulse test simulation platform can be built, and compared with no buffer circuit and single capacitor buffer circuit. The above ...
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