DRAM memory chip three-dimensional integrated packaging method and structure
A memory chip, three-dimensional integration technology, applied in the direction of electrical components, transistors, electric solid-state devices, etc., can solve the problems of high cost, high process difficulty, low yield rate of finished products, etc., and achieve low packaging cost, enhanced packaging structure strength, packaging The effect of high efficiency and yield
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Embodiment 1
[0058] The present invention provides a three-dimensional integrated packaging method for a DRAM memory chip, including: providing a mother chip and a sub-chip, and stacking and bonding the mother chip and the sub-chip. specific,
[0059] First, the master chip is formed by the following method:
[0060] A glass substrate 101 is provided, and a bonding layer 102 is spin-coated on the glass substrate 101, such as figure 1 The thickness of the glass substrate 101 is more than 50 μm, and the thickness of the bonding layer 102 is more than 0.1 μm;
[0061] Such as figure 2 As shown, the TSV transfer chip 105 and the storage chip 103 are placed on the bonding layer 102; the distance between the TSV transfer chip 105 and the storage chip 103 is more than 1 μm, and the number is not less than one; There is a metal pad 104 on the memory chip 103, the pad surface of which faces inward and is opposite to the bonding layer 102; the TSV transfer chip 105 has a TSV channel 106, and the TSV chan...
Embodiment 2
[0077] The present invention provides a DRAM memory chip three-dimensional integrated packaging structure, which is prepared by the DRAM memory chip three-dimensional integrated packaging method provided in Embodiment 1. The DRAM memory chip three-dimensional integrated packaging structure is as Figure 16 As shown, it includes a top layer, several middle layers, and a bottom layer that are sequentially bonded.
[0078] Specifically, the bottom layer includes a TSV transfer chip 105 and a memory chip 103 encapsulated by a plastic molding compound 107, an n-layer rewiring 108 and bumps 109 are formed on the front of the bottom layer, and an adhesive layer 110 is made on the back; The n-layer rewiring 108 on the front connects the TSV transfer chip 105 and the storage chip 103 in the bottom layer; the distance between the TSV transfer chip 105 and the storage chip 103 in the bottom layer is more than 1 μm.
[0079] The intermediate layer includes a TSV transfer chip 205 and a memory c...
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Abstract
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