Self-aligned quadruple pattern and method for manufacturing semiconductor device

Abstract

The invention relates to a method for manufacturing a self-aligned quadruple pattern and a semiconductor device, comprising: sequentially forming a second mandrel layer, a second anti-reflection layer, a first mandrel layer and a first anti-reflection layer on a target etching layer layer, wherein the first anti-reflection layer has etching selectivity relative to the second anti-reflection layer; etch the first anti-reflection layer and the first mandrel layer to form a first mandrel pattern; in the Covering the first sidewall material layer on the first mandrel pattern; etching the first sidewall material layer and the first mandrel pattern in the horizontal direction to form a first sidewall; using the first sidewall as a mask Etching the second anti-reflection layer and the second mandrel layer to form a second mandrel pattern; covering the second side wall material layer on the second mandrel pattern; and etching the second mandrel layer in the horizontal direction. Two sidewall material layers and the second mandrel pattern are used to form a second sidewall on the target etching layer. The invention can improve line edge roughness and line width roughness.

Description

technical field [0001] The invention relates to the field of manufacturing integrated circuits, in particular to a method for manufacturing a self-aligned quadruple pattern and a method for manufacturing a semiconductor device. Background technique [0002] In the field of integrated circuits, lithography (Lithography) technology is the core of IC manufacturing, and its main function is to transfer the chip circuit pattern on the mask to the silicon wafer. Photolithography processes define the dimensions of semiconductor devices. Current semiconductor devices have increasingly smaller requirements for critical dimensions. For example, the channel length of field effect transistors has reached the deep submicron range. The smaller the feature size, the higher the integration of the chip, the better the performance, and the lower the power consumption. However, as the size shrinks, the effect on the line edge roughness (LER) of the pattern caused by the photoresist exposure ...

AI Technical Summary

Problems solved by technology

However, these technologies are costly

Moreover, 193nm immersion lithography technology cannot realize the process node of 14nm and below

Although EUV lithography technology can achieve smaller process nodes, EUV photoresist still faces great difficulties and challenges in terms of resolution, line edge roughness and sensitivity, and has not yet achieved mass production capacity.

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