Manufacturing method of split gate MOSFET

Abstract

The invention discloses a manufacturing method of a split gate MOSFET. The manufacturing method comprises the following steps: 1, forming an epitaxial layer on a substrate; 2, depositing an ONO structure on a first main surface; 3, performing etching to form a groove; 4, removing a second oxide layer; 5, forming a third oxide layer in a trench; 6, forming separation gate polycrystalline silicon inthe trench; 7, removing a third oxide layer on a side wall of the upper part of the trench, so that the top of the separation gate polysilicon is higher than the reserved third oxide layer; 8, forming an inter-polysilicon isolation oxide layer in a high-density plasma chemical vapor deposition mode, forming a side wall oxide layer on the side wall of the trench, and forming a thick oxide layer onthe first nitride layer; 9, removing a side wall oxide layer; 10, removing the first nitride layer so as to peel off the thick oxide layer. According to the method, the inter-polycrystalline siliconisolation oxide layer meeting the process requirements is formed on the separation gate polycrystalline silicon at a time in an HDPCVD mode, and the thickness of the inter-polycrystalline silicon isolation oxide layer can be accurately controlled.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a split-gate MOSFET. Background technique [0002] Trench power MOSFET is a new high-efficiency switching device developed after planar VDMOS. It is widely used in the field of power electronics because of its high input impedance, small driving current, fast switching speed, and good high-temperature characteristics. High breakdown voltage, high current, and low on-resistance are the most critical indicators of power MOSFETs. The breakdown voltage is related to the value of on-resistance. In the process of MOSFET design, high breakdown voltage and low on-resistance cannot be obtained at the same time. Balance each other between the two. [0003] In order to obtain a higher breakdown voltage and lower on-resistance as possible, a new type of split-gate structure MOSFET device has emerged. Compared with the ordinary trench MOSFET structure, its m...

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Problems solved by technology

[0005] 1. Poor insulation of the polysilicon isolation oxide layer (IPO, inter-poly oxide) between the source and the gate leads to an increase in gate-source leakage current Igss;

[0006] 2. The overlapping area between the source and the gate is too large, and the thickness of the isolation oxide layer between polysilicon is insufficient, resulting in a substantial increase in the capacitance Cgs between the source and the gate

[0007] The main cause of the above-mentioned shortcoming is that, in the production technology of prior art, as Figure 2A to Figure 2D As shown, after wet etching removes the separation gate oxide layer on the side wall of the trench, the surface of the separation gate polysilicon will be higher than the separation gate oxide layer, and a recessed structure will be formed on both sides of the separation gate polysilicon, resulting in the subsequent formation of the gate oxide layer. When the isolation oxide layer between polysilicon and polysilicon is formed, because the thickness of the isolation oxide layer between polysilicon is very thin, it will form a "ㄇ" shape, which makes the insulation between the source and the gate poor and the overlapping area is too large, resulting in the above disadvantages

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