Clock data recovery method and circuit

Abstract

An embodiment of the invention discloses a clock data recovery method and a clock data recovery circuit. The clock data recovery method comprises the following steps: each voltage-controlled oscillator determines whether the frequency of a periodic signal generated by the voltage-controlled oscillator is the same as that of a received reference signal; if the frequency of the periodic signal of the current voltage-controlled oscillator is different from that of the received reference signal, the current voltage-controlled oscillator inputs the generated first frequency modulation signal to a DDS signal generator; the DDS signal generator performs fractional frequency division processing on the first frequency modulation signal to obtain a second frequency modulation signal, and inputs thesecond frequency modulation signal to the phase discriminator; the phase discriminator performs voltage regulation on the current voltage-controlled oscillator based on the second frequency modulationsignal so as to perform clock data recovery based on the regulated signal generated by the current voltage-controlled oscillator. According to the method disclosed in the invention, high-speed clockdata recovery can be realized, the quality of recovered clock signals is improved, and wide-frequency coverage can be realized.

Description

technical field [0001] The invention relates to the technical field of network communication, in particular to a clock data recovery method and circuit. Background technique [0002] With the continuous development of network communication technology, the transmission distance and transmission speed of the backbone network are also increasing. In order to ensure the efficient transmission of network data, how to realize the recovery of the clock signal and the data signal becomes particularly important. [0003] At present, a clock signal and a data signal are recovered by using a CDR (Clock and Data Recovery, high-speed clock data recovery) circuit. Specifically, the CDR circuit includes two parts: a clock recovery (CR, Clock Recovery) circuit and a data recovery (DR, Data Recovery) circuit, and DR can be subdivided into a clock data phase adjustment (phase alignment, phase alignment) circuit and a data sampling circuit. decision circuit. When performing long-distance hi...

AI Technical Summary

Problems solved by technology

In this way, since the network signal is regenerated by the CDR circuit, its phase jitter will be amplified

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