Multi-die FPGAs implementing clock trees using active silicon connection layers

Abstract

The present application discloses a multi-die FPGA utilizing an active silicon connection layer to implement a clock tree. The multi-die FPGA includes several FPGA dies, and these several FPGA dies are stacked on the same silicon connection layer. Interconnection communication is realized through the cross-die connection inside the silicon connection layer; source devices are also arranged in the silicon connection layer to build a balanced clock tree, and the clock signal is pushed to each FPGA die through the balanced clock tree, so that the clock of each FPGA die Synchronization, the balanced clock tree in the silicon connection layer can balance the delay of the clock signal reaching each FPGA die, reduce the problem of excessive clock skew in cross-die communication, speed up design convergence, and improve the performance of multi-die FPGAs .

Description

Multi-die FPGAs for Clock Trees Using Active Silicon Link Layers technical field The present invention relates to semiconductor technology field, especially a kind of multi-die utilizing active silicon connection layer to realize clock tree FPGA. Background technique FPGA (Field Programmable Gate Array, Field Programmable Logic Gate Array) is a hardware programmable The programmed logic devices are not only used in mobile communications, data centers and other fields, but also widely used in integrated circuit design. Prototype verification can effectively verify the correctness of circuit functions and speed up circuit design. Prototype verification requires the use of The programmable logic resources inside the FPGA realize circuit design. With the continuous increase in the scale of integrated circuits and the realization of complex functions At present, the demand for the number of programmable logic resources of FPGA continues to increase, and the subsequent ...

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Problems solved by technology

However, the above two patents are limited by the defects of the chip itself and the structural design. Both of them can only interconnect two adjacent IC dies arranged side by side, and can only realize signal interconnection in a single direction. Very limited

In addition, the balance of cross-die clock signals in this multi-die structure is also a problem that has to be considered, and it is also a big challenge. The conventional approach may be to connect the clock inputs between the die in series, but this It will cause the clock to be out of sync, and the clock skew will be very large, which will seriously affect the performance of cross-die design

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