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A preparation method of TSV passive interposer for three-dimensional system-in-package

A system-level packaging and adapter board technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., can solve the problems of silicon material waste and inability to recycle, and achieve cost-saving effects

Active Publication Date: 2022-04-08
FUDAN UNIV +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, for the thinning of silicon wafers, mechanical grinding is usually used, in which a considerable thickness of silicon material will be removed but cannot be recycled, resulting in a large waste of silicon material

Method used

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  • A preparation method of TSV passive interposer for three-dimensional system-in-package
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Embodiment Construction

[0017] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. It should be understood that the specific The examples are only used to explain the present invention, not to limit the present invention. The described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0018] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "vertical" and "horizontal" are based on the orientation or positional relation...

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Abstract

The invention discloses a preparation method for a TSV passive adapter plate used for three-dimensional system-level packaging. The ion implantation process is used to implant low-energy ions into the single crystal silicon substrate to a shallow depth, and then perform high-temperature annealing to form a layer of silicon compound inside the silicon substrate, so that the silicon compound divides the silicon substrate into the top layer of silicon above and the bottom layer of silicon. bulk silicon. Then, a certain thickness of single crystal silicon is grown on the surface of the top layer of silicon by molecular beam epitaxy as a substrate. The invention can make full use of the silicon material, save costs, and at the same time facilitate the realization of high-density packaging of chips.

Description

technical field [0001] The invention relates to the field of integrated circuit packaging, in particular to a method for preparing a TSV passive adapter board for three-dimensional system-level packaging. Background technique [0002] With the rapid development of integrated circuit technology, microelectronic packaging technology has gradually become the main factor restricting the development of semiconductor technology. In order to realize the high density of electronic packaging, obtain better performance and lower overall cost, technicians have developed a series of advanced packaging technologies. Among them, the three-dimensional system-in-package technology has good electrical performance and high reliability, and can achieve high packaging density at the same time, and is widely used in various high-speed circuits and miniaturized systems. Through Silicon Via (TSV) interposer technology is a new technology for interconnection of stacked chips in three-dimensional i...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L21/265H01L21/02H01L23/48
CPCH01L21/76898H01L23/481H01L21/26506H01L21/02532H01L21/02631H01L2224/14181
Inventor 朱宝陈琳孙清清张卫
Owner FUDAN UNIV
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