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Cellular structure of silicon carbide MOSFET device, preparation method of structure and silicon carbide MOSFET device

A silicon carbide and cell technology, which is used in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as the on-resistance trade-off relationship that cannot be achieved in gate oxide layer electric field stress devices

Active Publication Date: 2020-11-13
ZHUZHOU CRRC TIMES SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In view of the above problems, the present disclosure provides a cell structure of a silicon carbide MOSFET device, its preparation method and a silicon carbide MOSFET device, which solves the problem of the electric field stress and device failure of silicon carbide MOSFETs in the prior art that cannot achieve a good gate oxide layer. The technical issue of the trade-off relationship between on-resistance

Method used

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  • Cellular structure of silicon carbide MOSFET device, preparation method of structure and silicon carbide MOSFET device
  • Cellular structure of silicon carbide MOSFET device, preparation method of structure and silicon carbide MOSFET device
  • Cellular structure of silicon carbide MOSFET device, preparation method of structure and silicon carbide MOSFET device

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Embodiment 1

[0063] Such as figure 2 As shown, an embodiment of the present disclosure provides a cellular structure 200 of a silicon carbide MOSFET device, including a substrate 201, a drift layer 202, a well region 203, a source region 204, an enhancement region 205, a JFET region 206, a shield region 207, a gate Extreme oxide layer 208 , gate 209 , interlayer dielectric layer 210 , source metal layer 211 , and drain metal layer 212 .

[0064] Exemplarily, the substrate 201 is a silicon carbide substrate 201 of the first conductivity type. The thickness of the substrate 201 is thicker, the ion doping concentration is higher, and the ion doping concentration is greater than 1E19cm -3 .

[0065] The drift layer 202 is a drift layer 202 of the first conductivity type, located above the substrate 201, with an ion doping concentration of about 1E14 to 5E16cm -3 , it needs to be optimized according to the withstand voltage of the chip. Wherein, on both sides of the cellular structure 200,...

Embodiment 2

[0079] On the basis of the first embodiment, this embodiment provides a method for preparing a cell structure 200 of a silicon carbide MOSFET device. image 3 It is a schematic flowchart of a method for preparing a cell structure 200 of a silicon carbide MOSFET device shown in an embodiment of the present disclosure. Figure 4-Figure 10 It is a schematic diagram of the cross-sectional structure formed by the relevant steps of the manufacturing method of the cellular structure 200 of a silicon carbide MOSFET device shown in the embodiment of the present disclosure. Below, refer to image 3 and Figure 4-Figure 10 The detailed steps of an exemplary method of the method for manufacturing the cellular structure 200 of the silicon carbide MOSFET device proposed by the embodiment of the present disclosure will be described.

[0080] Such as image 3 As shown, the method for preparing the cell structure 200 of the silicon carbide MOSFET device in this embodiment includes the follo...

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Abstract

The invention provides a cellular structure of a silicon carbide MOSFET device, a preparation method of the cellular structure and the silicon carbide MOSFET device. The cellular structure comprises afirst conductive type drift layer located above a substrate; side grooves are downwards formed in the positions, at the two sides of the cellular structure, of the surface of the drifting layer, so that a boss is formed in the center of the cellular structure, of the surface of the drifting layer; a second conductive type well region is positioned under the side grooves; a first conductive type source region is positioned in the surface of the well region; and a second conductive type shielding region is arranged in the drift layer and is positioned under the top and the side wall of the bossand the side, close to the boss, of the bottom of the side groove. Due to additional arrangement of the shielding region, the electric field stress of the gate oxide layer of the device in a blockingstate can be greatly reduced, and the reliability of long-term use is greatly improved. The shielding region has little influence on the conduction characteristic of the device, so that a good compromise relationship between the electric field stress of the gate oxide layer and the conduction resistance can be realized.

Description

technical field [0001] The present disclosure relates to the technical field of semiconductor devices, in particular to a cell structure of a silicon carbide MOSFET device, a preparation method thereof, and a silicon carbide MOSFET device. Background technique [0002] Silicon carbide (SiC) is a new wide-bandgap semiconductor material with excellent physical, chemical and electrical properties. The breakdown electric field strength of silicon carbide is 10 times that of traditional silicon, the thermal conductivity is 3 times that of silicon, and it has a higher switching frequency, which can reduce the loss and volume of energy storage components in the circuit. Theoretically, SiC devices can work in a high-temperature environment above 600°C, and have excellent radiation resistance, which greatly improves their high-temperature stability. This makes SiC-based power semiconductor devices very attractive and promising for high-power and high-temperature applications. Among...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L29/78H01L21/336
CPCH01L29/0615H01L29/0684H01L29/78H01L29/66477Y02B70/10
Inventor 王亚飞陈喜明李诚瞻罗海辉
Owner ZHUZHOU CRRC TIMES SEMICON CO LTD
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