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Reliable polysilicon-silicide grid laminate with reduced sheet resistance

A conductor and gate technology, applied in the field of transistors with polysilicon-silicide gates, can solve problems such as device performance degradation

Inactive Publication Date: 2003-09-03
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, these techniques undesirably increase gate resistance, resulting in degraded device performance

Method used

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  • Reliable polysilicon-silicide grid laminate with reduced sheet resistance
  • Reliable polysilicon-silicide grid laminate with reduced sheet resistance
  • Reliable polysilicon-silicide grid laminate with reduced sheet resistance

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Embodiment Construction

[0015] The present invention relates to a reliable polysilicon-silicide gate with reduced sheet resistance. To facilitate the discussion of the present invention, it is described by means of a memory IC. However, the invention is clearly broader and applies to integrated circuits in general. Provided here is a description of a DRAM cell.

[0016] refer to figure 1 , represents a trench capacitance DRAM cell 100 . The trench capacitive DRAM cell is described in, for example, "A 0.6μm" by Nesbit et al. 2 256Mb Trench DRAM With Self-aligned Buried Strap (BEST)", IEDM 93-627 has instructions, which is hereby incorporated by reference in any case. Although a trench capacitance DRAM cell is shown, the present invention It is not limited thereto. For example, a stack capacitor type DRAM cell can also be used. Usually, an array of the elements constitutes a DRAM integrated circuit after word lines and bit lines are connected to each other.

[0017] Illustratively, DRAM cell 101 i...

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Abstract

Formation of a gate having a polysilicon and silicide layer thereover with reduced resistance and reduced thickness is provided. The polysilicon layer is annealed to diffuse the dopants out from the surface to reduce the dopant concentration to below the level which causes metal rich interface. Thus, a metal silicide layer can be deposited without an intrinsic poly cap layer or requiring the poly to having a decreased dopant concentration. As such, a thinner gate stack having lower sheet resistance and improved reliability is achieved.

Description

technical field [0001] The field of the invention relates generally to semiconductor fabrication, and specifically to transistors with polysilicon-silicide gates. Background technique [0002] In device fabrication, insulating layers, semiconductor layers, and conductor layers are formed on one substrate. These layers are patterned to form patterned areas and blank areas. The engraved patterned areas and blank areas can form devices such as transistors, capacitors and resistors. These devices are then interconnected to achieve the required electrical functions, creating an integrated circuit (IC). [0003] In order to reduce the sheet resistance (sheet resistance), the metal oxide semiconductor transistor (MOS) uses a polysilicon silicide (polycide) gate, and the polysilicon-silicide (polycide) gate is made of metal silicide such as tungsten silicide (WSi x ) placed on heavily doped polysilicon (poly). Typically, polysilicon is doped with phosphorus (P). Polysilicon sho...

Claims

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Application Information

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IPC IPC(8): H01L21/28H01L21/336H01L21/8234H01L29/49H01L29/78H10B12/00
CPCH01L21/823443H01L27/10873H01L29/4933H01L21/28061H10B12/05H01L29/40H01L27/04
Inventor 马丁·施莱姆斯马赛厄·勒格
Owner INFINEON TECH AG
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