Preparation method of efficient monocrystalline silicon SE-PERC battery piece

Abstract

The invention discloses a preparation method of an efficient monocrystalline silicon SE-PERC battery piece. The preparation method comprises the steps of raw material silicon wafer selection, texturing, diffusion, laser doping, phosphorosilicate glass removal, passive film deposition, passive antireflection film deposition, back laser grooving, silk-screen printing and sintering. Specifically, the raw material silicon wafer is a silicon wafer prepared through a wire cutting method, cutting lines on the silicon wafer are set to be in the X direction, the conveying direction of the silicon wafer is controlled to be in the Y direction in the phosphorosilicate glass removal step, and an included angle is formed between the Y direction and the X direction. The preparation method provided by the invention can effectively improve the overall conversion efficiency of the battery piece.

Description

technical field [0001] The invention relates to the technical field of production and manufacture of monocrystalline silicon cells, in particular to a method for preparing high-efficiency monocrystalline silicon SE-PERC cells. Background technique [0002] The biggest difference between PERC batteries (Passivated Emitter and Rear Cell) and conventional batteries is that the back surface of the battery is passivated with a dielectric film, and local metal contacts are used to reduce the recombination of the back surface and increase the open circuit voltage. Increase the reflection of the back surface, improve the short-circuit current, and thus improve the efficiency of the battery. Due to its relatively simple process and less cost increase, PERC battery is the mainstream production process at present and in the future. [0003] PERC technology is highly compatible with existing production lines and is easy to upgrade production lines. For example, SE-PERC technology is ba...

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Problems solved by technology

[0006] However, as we all know, square resistance and junction depth are a reflection of doping concentration. High square resistance means less doping and shallower junction depth, which will lead to higher Rs and increased contact resistance, which will affect the conversion efficiency of the cell. ;Low square resistance means more doping, deeper junction depth, too much doping will cause dead layer, resulting in a serious decline in passivation quality

During the doping process of gallium-doped silicon wafers, if the doping concentration of the silicon substrate in the base region is increased, it is beneficial to reduce the saturation dark current. However, if the doping concentration is too high, the minority carrier diffusion length will be shortened. When the minority carrier diffusion length When the thickness of the base region is smaller than the thickness of the base region, the photogenerated carriers can no longer be effectively collected, so a compromise doping concentration of the silicon substrate is required. At present, there is no uniform standard for the square resistance of gallium-doped silicon wafers, and the existing shallow junction has high square resistance. The resistivity standard of 0.5-1.5Ω·cm in the diffusion process is only applicable to boron-doped silicon wafers, not to gallium-doped silicon wafers

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