Three-dimensional memory and preparation method thereof

Abstract

The invention provides a three-dimensional memory and a preparation method thereof. The preparation method of the three-dimensional memory comprises the following steps of: preparing an intermediate comprising a channel structure, a gate gap structure and a step structure; providing a first substrate, and combining a first surface of the first substrate with the front surface, on which the channel structure, the gate gap structure and the step structure are formed, of the intermediate; and forming a peripheral circuit on a second surface of the first substrate opposite to the first surface. According to the preparation method, the electrical property of the peripheral circuit can be effectively prevented from being reduced due to the thermal influence of the front surface forming process, so that the combined memory and peripheral circuit chip can jointly resist the stress generated by each film layer in the three-dimensional memory, and meanwhile, the technical process and the preparation period for preparing the three-dimensional memory are simplified; under the condition that the number of stacked layers of the three-dimensional memory is increased, a corresponding preparation process can be realized without replacing a machine table.

Description

technical field [0001] The present application relates to the field of semiconductor design and manufacturing, and more specifically, to a structure of a three-dimensional memory (3D NAND) and a manufacturing method thereof. Background technique [0002] In the traditional three-dimensional memory manufacturing process, the stacked structure of the memory array is built on the substrate (for example, a silicon wafer), and as the number of stacked layers increases, the dielectric film layer (for example, a silicon oxide layer) included in the three-dimensional memory , silicon nitride layers, polysilicon layers, and tetraethylorthosilicate (TEOS) layers) are becoming increasingly complex. When multiple layers are stacked, stress may build up in the wafer and cause deformation of the dielectric film layers described above. [0003] In addition, the thermal influence of three-dimensional memory manufacturing processes such as etching, filling and heat treatment may further agg...

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Problems solved by technology

[0003] In addition, the thermal influence of three-dimensional memory manufacturing processes such as etching, filling and heat treatment may further aggravate the problem of deformation of the dielectric thin film layer, which may lead to structural instability of the memory device, causing problems such as warpage, and further, As a result, peripheral circuit chips cannot be miniaturized, and problems such as electrical performance degradation occur

When the deformation of the dielectric film layer exceeds a certain limit, it may eventually cause the wafer to bend or the corresponding process cannot be performed in the machine

As the number of stacked layers increases, due to factors such as stress, it is difficult to align the upper and lower channel holes, and the overlay accuracy (OVL) of the upper and lower channel holes may be offset. Therefore, in When performing deep hole etching, the functional layer at the junction of the upper and lower channel holes will be destroyed, thereby affecting the electrical properties of the prepared three-dimensional memory

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