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Semiconductor structure and fabrication method thereof

A manufacturing method and semiconductor technology, applied in the direction of semiconductor devices, transistors, electric solid devices, etc., can solve problems such as poor bit line morphology, achieve the effects of flat side walls, vertical morphology, and improved electrical properties

Active Publication Date: 2022-04-12
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present invention provides a semiconductor structure and a manufacturing method thereof, which are used to solve the problem of poor morphology of the bit lines formed in the prior art, so as to improve the yield rate of the semiconductor structure with the bit lines and improve the performance of the semiconductor structure

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  • Semiconductor structure and fabrication method thereof
  • Semiconductor structure and fabrication method thereof
  • Semiconductor structure and fabrication method thereof

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Embodiment Construction

[0050] The specific implementation of the semiconductor structure provided by the present invention and the manufacturing method thereof will be described in detail below in conjunction with the accompanying drawings.

[0051] This specific embodiment provides a method for fabricating a semiconductor structure, with figure 1 It is a flow chart of the manufacturing method of the semiconductor structure in the specific embodiment of the present invention, with Figures 2A-2N It is a schematic cross-sectional view of the main process in the process of manufacturing the semiconductor structure according to the specific embodiment of the present invention. Such as figure 1 , Figure 2A-Figure 2N As shown, the manufacturing method of the semiconductor structure provided in this specific embodiment includes the following steps:

[0052] Step S11, providing a substrate 20, which includes a polysilicon layer 221, a first conductive layer 223, a first dielectric layer 23, a mask laye...

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Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure includes: providing a substrate, and the substrate includes a polysilicon layer, a first conductive layer, a first dielectric layer, a mask layer and a sacrificial layer formed sequentially; wherein, the sacrificial layer has multiple a first trench distributed at intervals; forming a first insulating layer on the sacrificial layer; forming a protective layer, the protective layer covering only the surface of the first insulating layer above the top surface of the sacrificial layer; removing The first insulating layer located at the bottom of the first trench; removing the protective layer, part of the first insulating layer, the sacrificial layer and part of the mask layer to form a first pattern layer; The first pattern layer is a mask to remove part of the first dielectric layer, part of the first conductive layer, and part of the polysilicon layer to form a bit line structure. The present invention can obtain a bit line structure with flat sidewall and vertical appearance.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a manufacturing method thereof. Background technique [0002] DRAM (Dynamic Random Access Memory, DRAM) is a semiconductor device commonly used in electronic equipment such as computers, which is composed of a plurality of storage units, and each storage unit usually includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that the stored data can be read through the bit line. Data information in the capacitor, or write data information into the capacitor. [0003] As the feature size of semiconductor integrated circuit devices continues to shrink, the requirements for the...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/108H10B12/00
CPCH10B12/02H10B12/05
Inventor 于业笑刘忠明方嘉
Owner CHANGXIN MEMORY TECH INC