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Wafer-level welding process of multilayer adapter plate

A welding process, wafer-level technology, applied in the field of wafer-level welding process, can solve the problems of limited adapter board, limited application range of RF modules, and cannot be made too thick, and achieves the effect of increasing the total depth

Pending Publication Date: 2021-08-24
浙江集迈科微电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, the RF chip needs to be grounded and interconnected at the bottom of the adapter board, so it is necessary to dig a cavity on the adapter board to embed the RF chip and the auxiliary chip into the adapter board. Some chips are thicker, and the thickness of the adapter board There are also higher requirements, but the adapter board is often limited by the depth of TSV technology and cannot be made too thick, which greatly limits the application range of RF modules

Method used

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  • Wafer-level welding process of multilayer adapter plate
  • Wafer-level welding process of multilayer adapter plate
  • Wafer-level welding process of multilayer adapter plate

Examples

Experimental program
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Embodiment 1

[0029] A wafer-level welding process for a multilayer interposer, comprising the following steps:

[0030] Step S1, making TSV blind holes 102 on the surface of the silicon wafer 101, forming a passivation layer 103 on the surface of the silicon wafer 101 where the opening of the blind holes 102 is located, depositing a seed layer 107 on the passivation layer 103, and then electroplating to form TSV metal pillars 104 , and polishing the surface metal of the silicon wafer 101 to obtain a silicon wafer with TSV metal pillars 104;

[0031] Specifically, such as Figure 1a As shown, a TSV blind hole 102 is fabricated on the surface of a silicon wafer 101 by a photolithography process, the diameter of the hole is 10 μm, and the depth is 50 μm;

[0032] Such as Figure 1b As shown, silicon oxide is deposited on the surface of the silicon wafer 101 where the opening of the TSV blind hole 102 is located to form a passivation layer 103, and the thickness of the passivation layer 103 i...

Embodiment 2

[0045] A wafer-level welding process for a multilayer interposer, comprising the following steps:

[0046] Step S1, making a TSV blind hole 102 on the surface of the silicon wafer 101, forming a passivation layer 103 on the surface of the silicon wafer 101 where the opening of the blind hole 102 is located, depositing a seed layer 107 on the passivation layer 103, and then electroplating the TSV metal pillar 104, And polishing the surface metal of the silicon wafer 101 to obtain a silicon wafer with TSV metal pillars 104;

[0047] Specifically, a TSV blind hole 102 is formed on the surface of the silicon wafer 101 by a photolithography process, the diameter of the hole is 100 μm, and the depth is 200 μm;

[0048] Deposit silicon nitride on the surface of the silicon wafer 101 where the opening of the TSV blind hole 102 is located to form a passivation layer 103, the thickness of the passivation layer 103 is 10 μm;

[0049] Fabricate a seed layer 107 on the surface of the pass...

Embodiment 3

[0061] A wafer-level welding process for a multilayer interposer, comprising the following steps:

[0062] Step S1, making a TSV blind hole 102 on the surface of the silicon wafer 101, forming a passivation layer 103 on the surface of the silicon wafer 101 where the opening of the blind hole 102 is located, depositing a seed layer 107 on the passivation layer 103, and then electroplating the TSV metal pillar 104, And polishing the surface metal of the silicon wafer 101 to obtain a silicon wafer with TSV metal pillars 104;

[0063] Specifically, a TSV blind hole 102 is formed on the surface of the silicon wafer 101 by a photolithography process, the diameter of the hole is 800 μm, and the depth is 1000 μm;

[0064] The surface of the silicon wafer 101 where the opening of the TSV blind hole 102 is located is directly thermally oxidized to form a passivation layer 103, and the thickness of the passivation layer 103 is 80 μm;

[0065] The seed layer 107 is made on the surface of...

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Abstract

The invention relates to a wafer-level welding process of a multilayer adapter plate, which comprises the following steps of: manufacturing TSV blind holes on the surface of a silicon wafer, forming a passivation layer on the surface of the silicon wafer, depositing a seed layer on the passivation layer, then electroplating to form TSV metal columns, and polishing surface metal of the silicon wafer to obtain the silicon wafer with the TSV metal columns; thinning the back surface of the silicon wafer to expose the TSV metal columns on the back surface, and etching grooves in other areas; depositing a passivation layer on the surface of the silicon wafer on the surface of the groove, depositing a seed layer on the surface of the passivation layer, filling metal soldering tin in the groove through electroplating, and then removing the seed layer; and bonding the two silicon wafers with the metal soldering tin face to face, the fusing soldering tin after hot pressing, bonding passivation layers between the silicon wafers, and finally achieving welding between the two silicon wafers. According to the invention, double-layer adapter plate interconnection is realized by means of passivation layer bonding and metal fusion bonding, and the double-layer TSV metal columns are welded together, so that the depth of the TSV metal columns can be increased, and a subsequent module embedding process is facilitated.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a wafer-level welding process for a multilayer adapter board. Background technique [0002] At present, millimeter-wave radio frequency technology is developing rapidly in the semiconductor industry. It is widely used in high-speed data communications, automotive radar, airborne missile tracking systems, and space spectrum detection and imaging. It is expected that the market will reach 1.1 billion US dollars in 2018, becoming an emerging industry. New applications put forward new requirements for the electrical performance, compact structure and system reliability of the product. For the wireless transmitting and receiving system, it cannot be integrated into the same chip (SOC) at present, so it is necessary to integrate different chips including the radio frequency unit , filters, power amplifiers, etc. are integrated into an independent system to realize the functions...

Claims

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Application Information

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IPC IPC(8): H01L21/768
CPCH01L21/76898
Inventor 冯光建黄雷郭西高群
Owner 浙江集迈科微电子有限公司