Josephson junction device with submicron stack structure and preparation method of Josephson junction device

Abstract

The invention provides a Josephson junction device with a submicron stack structure and a preparation method of the Josephson junction device. The preparation method comprises the following steps: providing a substrate, and forming a Josephson junction stack structure on the substrate; forming an initial insulating layer to cover the substrate and the Josephson junction stack structure; performing first photoetching on the initial insulating layer right above the Josephson junction stack structure to form a first insulating ring; carrying out second photoetching on the residual insulating layer to form a second insulating ring; performing chemical mechanical polishing; forming a contact hole in the remaining insulating layer; and forming a top electrode lead-out layer and a bottom electrode lead-out layer. According to the invention, parasitic inductance can be effectively reduced, leakage current caused by opening a hole right above the junction region and limitation on the size of the junction region can be avoided, technical support is provided for preparing a sub-micron-size stack SNS Josephson junction device, junction capacitance can be reduced, influence caused by external magnetic field noise can be avoided, and the preparation yield can be improved and the preparation cost can be reduced.

Description

technical field [0001] The invention relates to the technical field of superconducting devices, in particular to a Josephson junction device with a submicron stack structure and a preparation method thereof. Background technique [0002] SNS Josephson junction is a sandwich structure composed of superconductor layer (S)-normal metal layer (N)-superconductor layer (S), which is the core component of many superconducting devices and circuits. Benchmarks, single magnetic flux quantum circuits, superconducting quantum interference devices, etc. have been widely used. Since the SNS Josephson junction has non-hysteretic and basically negligible inductance characteristics, it has the advantages of simple process, strong device stability and process repeatability. In single flux quantum (SFQ) circuit applications, the characteristic voltage V c (~I c R n ) and critical current density J c It is a characteristic parameter closely related to the highest operating frequency of the...

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Problems solved by technology

The number of Josephson junctions required in SFQ circuits can reach tens of thousands or even hundreds of thousands. If you want to increase the integration level and meet the needs of high-speed digital circuits, you need to further reduce the area occupied by each Josephson junction; During the working process of Josephson junction devices, hysteresis and flux pinning phenomena often occur due to the temperature rise caused by externally applied current, which is not conducive to the measurement in the experiment and the application in practice.

[0003] In the current preparation of stacked Josephson junctions, the device size depends on the limit of pattern exposure resolution. Although stepper projection lithography (stepper) can be used to achieve sub-micron limit resolution, due to the preparation of Josephson junctions In the process, it is necessary to open a small hole smaller than the junction area on the insulating layer above the Josephson junction to realize the connection between the wiring layer and the top electrode, so the photolithography resolution determines the size of the small hole, generally the size of the Josephson junction 0.5-1μm larger than the small hole, so the current process is difficult to achieve the preparation of submicron size Josephson junction

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