Submicron stack structure Josephson junction device and its preparation method

Abstract

The invention provides a Josephson junction device with a submicron stack structure and a preparation method thereof. The preparation method includes the steps of: providing a substrate, forming a Josephson junction stack structure on the substrate; forming an initial insulating layer covering the substrate and the Josephson junction stack structure; performing a first step on the initial insulating layer directly above the Josephson junction stack structure. Photolithographic etching to form a first insulating ring; performing a second photolithographic etching on the remaining insulating layer to form a second insulating ring; performing chemical mechanical polishing; forming a contact hole in the remaining insulating layer; forming The top electrode extraction layer and the bottom electrode extraction layer. The invention can effectively reduce the parasitic inductance and avoid the leakage current caused by opening the hole directly above the junction region and limit the size of the junction region, and provides technical support for the preparation of submicron-sized stacked SNS Josephson junction devices, and can also reduce the size of the junction region. Capacitance, avoiding the influence of external magnetic field noise, helps to improve the production yield and reduce the production cost.

Description

technical field [0001] The invention relates to the technical field of superconducting devices, in particular to a Josephson junction device with a submicron stack structure and a preparation method thereof. Background technique [0002] The SNS Josephson junction is a sandwich structure consisting of a superconductor layer (S) - a normal metal layer (N) - a superconductor layer (S), and is the core element that constitutes many superconducting devices and circuits. Benchmarks, single-flux quantum circuits, and superconducting quantum interference devices have been widely used. Since the SNS Josephson junction has non-hysteresis and basically negligible inductance characteristics, it has the advantages of simple process, strong device stability and process repeatability. In single-flux quantum (SFQ) circuit applications, the characteristic voltage V c (~I c R n ) and the critical current density J c It is a characteristic parameter closely related to the highest operati...

AI Technical Summary

Problems solved by technology

The number of Josephson junctions required in SFQ circuits can reach tens of thousands or even hundreds of thousands. If you want to increase the integration level and meet the needs of high-speed digital circuits, you need to further reduce the area occupied by each Josephson junction; During the working process of Josephson junction devices, hysteresis and flux pinning phenomena often occur due to the temperature rise caused by externally applied current, which is not conducive to the measurement in the experiment and the application in practice.

[0003] In the current preparation of stacked Josephson junctions, the device size depends on the limit of pattern exposure resolution. Although stepper projection lithography (stepper) can be used to achieve sub-micron limit resolution, due to the preparation of Josephson junctions In the process, it is necessary to open a small hole smaller than the junction area on the insulating layer above the Josephson junction to realize the connection between the wiring layer and the top electrode, so the photolithography resolution determines the size of the small hole, generally the size of the Josephson junction 0.5-1μm larger than the small hole, so the current process is difficult to achieve the preparation of submicron size Josephson junction

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