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Top gate structure all-solid-state memory transistor multivariable mask plate based on overlay technology

A mask and sub-mask technology, which is applied in the field of multi-variable masks of top-gate structure all-solid-state memory transistors, can solve the problems of unfavorable experimental data, difficult degradation, and high cost, and achieves simple equipment, easy control, and film formation. good effect

Pending Publication Date: 2022-01-11
GUILIN UNIVERSITY OF TECHNOLOGY +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] Memory transistors can realize the integration of computing and storage, which is expected to break through von Neumann's bottleneck and realize parallel processing of signals; microelectronic devices can also be used to simulate the function of biological synapses, stepping out of the first place in neuromorphic engineering and artificial neural networks (ANNS). step; at present, the overlay technology based on photolithography is an important method to realize multi-layer high-definition layout; the top-gate structure memory transistor belongs to multi-layer high-definition layout, which needs multiple exposures to complete, and each exposure layer Graphics need to use different masks; however, the materials corresponding to many masks are organic materials or liquid materials, which have technical problems of difficult degradation and packaging, and the current CMOS-based process tape-out costs are relatively high, so it is not possible to To get enough experimental data

Method used

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  • Top gate structure all-solid-state memory transistor multivariable mask plate based on overlay technology
  • Top gate structure all-solid-state memory transistor multivariable mask plate based on overlay technology
  • Top gate structure all-solid-state memory transistor multivariable mask plate based on overlay technology

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0051] Table 1 shows the two contact types of this embodiment and the eight different device sizes they contain: pure numbers indicate full contact devices, and numbers marked with "'" indicate partial contact devices.

[0052] Table 1

[0053]

[0054] figure 1 It is a diagram of the contact mode between the source and drain electrodes and the channel according to the device of this embodiment. Divided into full contact type and partial contact type, the purpose is to compare the influence of parasitic parameters between source-drain electrodes and channels on device performance.

[0055] figure 2 For some devices with a small gate size in this embodiment, it is necessary to draw an illustration of the Pad area for needle sticking. Because the diameter of the probe of the Keithley semiconductor tester is 10 μm, for the convenience of testing.

[0056] image 3 It is a diagram of the position of the registration mark in the mask plate (channel mask plate, source-drain...

Embodiment 2

[0140] With embodiment 1, difference is, the Li of grid electrolyte in the step (11) 3 PO 4 Change target sputtering atmosphere to N 2 , the power was changed to 38W, the time was 5400s, and 100nm thick LiPON was plated.

[0141] It has been verified by experiments that LiPON is more 3 PO 4 There is a more obvious advantage that the ionic conductivity of LiPON is higher than that of Li 3 PO 4 much higher.

[0142] In order to avoid the problem of process accuracy, in the preparation process of the above embodiments, each contact surface is overlapped by 3 μm to prevent gaps.

[0143] Effect verification:

[0144] (1) In Example 1, the channel material WO was prepared sequentially through photolithography-coating-exposure-development-sputtering-stripping 3 (blue) and source-drain electrode material Au (golden yellow), observe the micrograph ( Image 6 with Figure 7 ),in Image 6 It is a photomicrograph figure of the step (1) device in the effect verification of the ...

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Abstract

The invention relates to the field of semiconductor device manufacturing, in particular to a top gate structure all-solid-state memory transistor multivariable mask based on an overlay technology. The mask plate comprises three sub-masks, specifically, a channel mask, a source and drain electrode mask and a grid electrode mask, wherein the channel mask comprises eight different device sizes, each device size corresponds to two contact modes of the channel region and the source and drain electrode region, and 16 devices capable of forming contrast are formed. According to the invention, the needed thin film is prepared through the magnetron sputtering method which is simple in equipment, easy to control and good in film forming effect, the film preparing technology is compatible with the CMOS technology, and batch production of devices is facilitated. The materials of all parts are all-solid-state materials, and the inherent degradation and difficult packaging problems of organic materials and liquid materials can be solved.

Description

technical field [0001] The invention relates to the field of semiconductor device manufacturing, in particular to a multi-variable mask plate of an all-solid-state memory transistor with a top-gate structure based on overlay technology. Background technique [0002] Memory transistors can realize the integration of computing and storage, which is expected to break through von Neumann's bottleneck and realize parallel processing of signals; microelectronic devices can also be used to simulate the function of biological synapses, stepping out of the first place in neuromorphic engineering and artificial neural networks (ANNS). step; at present, the overlay technology based on photolithography is an important method to realize multi-layer high-definition layout; the top-gate structure memory transistor belongs to multi-layer high-definition layout, which needs multiple exposures to complete, and each exposure layer Graphics need to use different masks; however, the materials co...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G03F1/68G03F1/00G03F1/38G03F1/42G03F7/20
CPCG03F1/68G03F1/00G03F1/38G03F1/42G03F7/70633
Inventor 袁星星张宝林王丽萍董江辉
Owner GUILIN UNIVERSITY OF TECHNOLOGY
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