Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The forming method comprises the following steps: providing a substrate, a gate structure, a gate cap layer located on the top of the gate structure, source and drain doped regions located in the substrate at two sides of the gate structure, and a bottom dielectric layer located on the substrate at the side part of the gate structure; a source-drain interconnection layer penetrating through the bottom dielectric layer at the top of the source-drain doped region is formed, and a groove is defined by the top surface of the source-drain interconnection layer and the adjacent grid cap layer and used for forming a source-drain cap layer; ion doping is performed on the side wall of the gate cap layer through the groove, so that the etching selection ratio between the source-drain cap layer and the gate cap layer can be improved; after ion doping, forming a source-drain cap layer in the groove; forming a top dielectric layer covering the gate cap layer and the source-drain cap layer; forming a source-drain contact hole penetrating through the top dielectric layer and the source-drain cap layer; and forming a source-drain plug in the source-drain contact hole. According to the embodiment of the invention, the probability of short circuit or breakdown between the source-drain plug and the adjacent gate structure is reduced.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background technique [0002] With the continuous development of integrated circuit manufacturing technology, people's requirements for the integration and performance of integrated circuits are becoming higher and higher. In order to improve integration and reduce costs, the critical dimensions of components are getting smaller and the circuit density inside integrated circuits is increasing. This development makes the surface of the wafer unable to provide enough area to make the required interconnection lines. [0003] In order to meet the requirements of the interconnection line after the critical dimension is reduced, at present, the conduction between different metal layers or between the metal layer and the substrate is realized through the interconnection structure. The inte...

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Problems solved by technology

[0005] However, the current COAG process still has great challenges, and short-circuit or breakdown between the source-drain plug and the adjacent gate structure is prone to occur.

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