Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure and the semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method of the semiconductor structure comprises the steps of providing a substrate; forming a plurality of silicon columns on the substrate, wherein the plurality of silicon columns are arranged in an array; the silicon columns are preset to form active columns, and each active column comprises a first section, a second section and a third section which are sequentially connected in the first direction; gate oxide layers are formed on the side walls of the second section and the third section; a gate dielectric layer is formed on the gate oxide layer, the length of the gate dielectric layer is smaller than that of the gate oxide layer in the first direction, and the top surface of the gate dielectric layer is flush with the top surface of the third section. According to the invention, the gate dielectric layer is formed on the side wall of the gate oxide layer, the length of the gate dielectric layer is smaller than that of the gate oxide layer, and the top surface of the gate dielectric layer is flush with the top surface of the third section, so that the turn-off current of the semiconductor structure can be controlled, and the problems of gate-induced drain leakage current and inter-band tunneling can be reduced. And the performance and the yield of the semiconductor structure are effectively improved.

Description

technical field [0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a method for fabricating a semiconductor structure and a semiconductor structure. Background technique [0002] Dynamic random access memory (DRAM for short) is a semiconductor memory that writes and reads data at high speed and randomly, and is widely used in data storage devices or devices. Wherein, the dynamic random access memory includes a plurality of memory cells arranged repeatedly, each memory cell includes a transistor and a capacitor, and the capacitor is connected to the source and drain of the transistor through the capacitive contact area and the capacitive contact structure. As electronic products are increasingly becoming lighter, thinner, shorter, and smaller, the design of dynamic random access memory components is also developing toward the trend of high integration, high density, and miniaturization. [0003] With the development of semic...

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Problems solved by technology

[0003] With the development of semiconductor technology, the size of semiconductor devices is getting smaller and smaller, and problems such as Gate Induced Drain Leakage (GIDL) will have a greater adverse effect on the formation of semiconductor structures, reducing the performance of semiconductor structures. and yield

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