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Low-warping-rate double-layer stacked ceramic system and packaging method

A packaging method and warpage rate technology, applied in coatings, decorative arts, measuring devices, etc., can solve the problems of large volume ratio of structural parts, difficulty in controlling the yield, and bending of ceramic materials, so as to achieve easy control of process parameters and low Warpage rate, the effect of improving system integration

Pending Publication Date: 2022-03-25
中国船舶重工集团公司第七二三研究所
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] On the one hand, the currently designed stacked packaging components adopt an I-shaped structure. Although the packaging efficiency is high, this structure will cause large bending of the ceramic material during the sintering process, and the production yield is difficult to control. For example, the patent number (CN112466864A) "A three-dimensional stacked microwave component based on high temperature co-fired ceramics"
[0004] On the other hand, the method of stacking and assembling ceramic substrates first, and then encapsulating them with a metal shell, although the assembly reliability is good, but the volume of the packaged structural parts is relatively large, and it is difficult to package RF active circuit chips that require cavity design. No. (CN 107275317A) "A Three-dimensional Stacked Structure of Thin Film Ceramic Circuits"

Method used

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Embodiment Construction

[0024] The present invention will be further described below with reference to the accompanying drawings and specific examples.

[0025] Combine figure 1 , A low-laundering bilateral stacked ceramic system of the present embodiment includes a top layer package assembly A1, a bottom package assembly A3, a bottom layer package assembly A1, a top package assembly A1, and a bottom package assembly A3, a top package assembly Between the inter-layer BGA solder ball A2; the bottom layer package assembly A3 is connected to the printed plate A5 by the underlying BGA solder ball A4;

[0026] The bottom layer package assembly A3 is composed of a bottom layer cover B1, a bottom layer frame B2, a bottom ceramic base B3, a bottom layer chip, and a sheet B4; the bottom ceramic base B3 is composed of high temperature co-burning ceramic material; the bottom surrounding Box B2, the bottom layer cover B1 is made of a taperable material, and the bottom layer frame B2 is soldered in the underlying cer...

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Abstract

The invention discloses a low-warping-rate double-layer stacked ceramic system and a packaging method. The system comprises a top-layer packaging assembly, a bottom-layer packaging assembly and a printed board which are sequentially arranged from top to bottom. BGA solder balls are used for interconnection between the packaging assemblies and between the packaging assemblies and the printed board. The bottom-layer ceramic base is provided with a sealing cavity of a concave structure, and the top-layer ceramic base is provided with a protruding metal enclosure frame. And the ceramic base and the accessories are assembled by adopting a plurality of welding materials and a welding method with different temperature gradients, so that airtight packaging of the assembly is realized. The ceramic base adopts a concave cavity structure to form an upward warping compensation direction, and the embedded enclosure frame is arranged on the ceramic base at the bottom layer to support the ceramic material. The bottom is grounded in a large area to form a good heat conduction channel, an active chip with large heat productivity can be placed, the top layer enclosure frame and the top ceramic base are consistent in appearance, the area of a ceramic plane is utilized to the maximum extent, more components can be contained and assembled, and the system integration degree is improved.

Description

Technical field [0001] The present invention relates to the field of integrated circuit packaging, in particular, a low-laundering ratio double layer stacked ceramic system and packaging method. Background technique [0002] The system-level package is integrated into a package inside the plurality of electronic components, including active chips, passive devices, microelectromechanical systems, and the like to form a single standard package component. In order to improve integration, stacking technology is an important means such as miniaturization, high density, high speed interconnection, multi-function integration, but stacked package technology has many deficiencies while significantly increasing system integration and improving system functionality. [0003] On the one hand, the currently designed stacked package assembly uses a hologram structure, although the package is high, the structure can cause a ceramic material to produce a large bending process, and the yield of p...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/04H01L23/10H01L23/367H01L21/50H01L21/60B81B7/00B81C1/00
CPCH01L23/04H01L23/367H01L23/10H01L21/50H01L24/81B81B7/0009B81B7/0032B81C1/00015H01L2224/81986
Inventor 韦炜王勇孙彪张兴稳邢君费新星张建民
Owner 中国船舶重工集团公司第七二三研究所
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