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Trench gate semiconductor device and manufacturing method thereof

A technology of semiconductor and trench gate, which is applied in the field of trench gate semiconductor devices and its manufacturing, and can solve the problems of SiC MOSFET threshold voltage being too large and insulating gate dielectric layer becoming thicker, etc.

Pending Publication Date: 2022-04-01
BYD SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0015] The technical problem to be solved by the present invention is to provide a trench gate semiconductor device and its manufacturing method for the problem that the insulating gate dielectric layer of the existing trench gate semiconductor device becomes thicker, resulting in a larger threshold voltage of SiC MOSFET

Method used

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  • Trench gate semiconductor device and manufacturing method thereof
  • Trench gate semiconductor device and manufacturing method thereof
  • Trench gate semiconductor device and manufacturing method thereof

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preparation example Construction

[0074] On the other hand, if Figure 2a to Figure 2l As shown, the present invention provides a method for preparing a trench gate semiconductor device, comprising the following steps:

[0075] S1. Etching and forming a trench 207 on the semiconductor substrate of the first conductivity type;

[0076] S2, forming a tunneling layer 208 in the insulating gate dielectric layer in the trench 207;

[0077] S3, forming a storage layer 209 in an insulating gate dielectric layer on the tunneling layer 208;

[0078] S4, forming a barrier layer 210 in the insulating gate dielectric layer on the storage layer 209;

[0079] S5 , depositing polysilicon in the trench 207 to form a gate electrode region 211 .

[0080] In this embodiment, the tunneling layer 208, the storage layer 209, and the barrier layer 210 are sequentially deposited inside the trench 207 to form the insulating gate dielectric layer with a certain thickness. The insulating gate dielectric layer is removed to reduce it...

Embodiment 1

[0105] In this embodiment, the first conductivity type is N type, and the second conductivity type is P type.

[0106] S1, providing an N-type substrate region 201 and an N-type epitaxial region 202, the doping concentration of the epitaxial region 202 is 10 13 cm -3 , with a thickness of 6 μm;

[0107] S2. A P-type well region 203 is formed by epitaxy or ion implantation on the epitaxial region 202, and a P+ contact region 204 and an N+ source region 205 are formed by ion implantation in the surface selective region of the well region 203. The P-type well region 203 doping concentration is 10 16 cm -3 , the thickness is 0.5 μm, and the doping concentration of the P+ contact region 204 is 10 18 cm -3 , the thickness is 0.2 μm, and the doping concentration of the N+ source region 205 is 10 18 cm -3 , with a thickness of 0.2 μm;

[0108] S3, forming a selective region by light development at the N+ source region 205, performing dry etching to form a trench 207, the etchi...

Embodiment 2

[0117] In this embodiment, the first conductivity type is N type, and the second conductivity type is P type.

[0118] S1, providing an N-type substrate region 201 and an N-type epitaxial region 202, the doping concentration of the epitaxial region 202 is 10 17 cm -3 , with a thickness of 500 μm;

[0119] S2. A P-type well region 203 is formed by epitaxy or ion implantation on the epitaxial region 202, and a P+ contact region 204 and an N+ source region 205 are formed by ion implantation in the surface selective region of the well region 203. The P-type well region 203 doping concentration is 10 18 cm -3 , the thickness is 50 μm, and the doping concentration of the P+ contact region 204 is 10 21 cm -3 , the thickness is 50 μm, and the doping concentration of the N+ source region 205 is 10 21 cm -3 , with a thickness of 50 μm;

[0120] S3, forming a selective region at the N+ source region 205 by light development, performing dry etching to form a trench 207, the etchin...

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Abstract

The invention belongs to the field of electrical elements, and particularly relates to a trench gate semiconductor device and a manufacturing method thereof.The trench gate semiconductor device comprises a semiconductor substrate, a gate electrode area and an insulated gate dielectric layer, a trench is formed in the semiconductor substrate, and the insulated gate dielectric layer is located between the gate electrode area and the semiconductor substrate; in the direction from the semiconductor substrate to the gate electrode area, the insulated gate dielectric layer sequentially comprises a tunneling layer used for charge tunneling in a strong electric field, a storage layer used for capturing holes and a barrier layer used for preventing charges from further tunneling to the gate electrode area. In the invention, due to the three layers of structures with different functions of the insulated gate dielectric layer, the insulated gate dielectric layer can be provided with additional positive charges, so that the problem that the threshold voltage of the device is increased due to the thickening of the insulated gate dielectric layer is solved. And meanwhile, the effect of ensuring that the threshold voltage of the device is not increased while the insulated gate dielectric layer is thickened to reduce the electric field intensity and improve the long-term reliability of the device is achieved.

Description

technical field [0001] The invention belongs to the field of electrical components, in particular to a trench gate semiconductor device and a manufacturing method thereof. Background technique [0002] Silicon carbide (SiC) is a new generation of wide-bandgap semiconductor materials. Its critical breakdown electric field 10 times that of silicon, high saturation drift rate and high thermal conductivity and other excellent material properties make the performance of power electronic devices based on SiC materials far away. It is far superior to Si-based materials, and has broad application prospects especially in high voltage and high power. Trench gate SiC MOSFETs have lower on-resistance than planar gates, and become the development direction of SiC MOSFETs in the future. The cross-sectional structure of the existing trench gate SiC MOSFET is as follows Figure 1j As shown, it mainly includes a substrate region, an epitaxial region, a well region, a contact region, a sourc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/792H01L21/336H01L29/423
Inventor 卢汉汉吴海平
Owner BYD SEMICON CO LTD