Heterojunction bipolar transistor with GAA structure and preparation method thereof

Abstract

The invention provides a heterojunction bipolar transistor with a GAA structure and a preparation method of the heterojunction bipolar transistor, the transistor is a small-size device, and the Si / SiGe heterojunction bipolar transistor is prepared by mainly utilizing a process of a full-surrounding gate field effect transistor (GAAFET). The emitter region and the base region of the structure form a full-surrounding heterogeneous emitter junction, and the base region and the collector region form a full-surrounding collector junction, so that the injection efficiency of the emitter junction and the carrier extraction capability of the collector region are effectively improved. For the Si / SiGe heterojunction, carriers can be effectively controlled by adjusting the change of the band gap width of the SiGe material; by improving the doping concentration of the SiGe base region, the device can obtain relatively high Early voltage, the base resistance is reduced, and the large injection effect is weakened; by reducing the thickness of the base region, the transition time of the base region is greatly shortened, and the excellent performance of ultrahigh frequency, ultrahigh speed and low noise can be realized.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a heterojunction bipolar transistor with a GAA structure and a preparation method thereof. Background technique [0002] The essence of the development history of semiconductor integrated circuit technology is the history of transistor size reduction. From the 10μm planar structure in the 1970s to the 22nm-FinFET three-dimensional structure in 2012, and then to the 5nm-FinFET, Moore's Law has been followed step by step. After 5nm, the FinFET structure is difficult to meet the electrostatic control required by transistors. In 2019, Samsung made it clear that it will apply Gate-All-Around FET technology at the next technology node 3nm. [0003] The new GAA structure can achieve better control of the field effect transistor channel, because the contact area between the gate and the channel is larger, from the three-sided contact of the FinFET structure to the four-si...

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Problems solved by technology

After 5nm, the FinFET structure is difficult to meet the electrostatic control required by transistors. In 2019, Samsung made it clear that it will apply Gate-All-Around FET technology at the next technology node 3nm.

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