Many-core definable distributed shared storage structure

Abstract

A many-core definable distributed shared storage structure comprises an internal data bus system, a routing unit, processor cores, a network interface unit and a memory module. A routing unit is arranged at the intersection of the transverse bidirectional data line and the longitudinal bidirectional data line; the processor core is connected with the routing unit through the network interface unit, and the routing unit and the network interface unit are connected through a processor core storage access bus; and the memory module is directly connected with the routing unit. A routing table is integrated in the network interface unit, a destination physical coordinate position is directly inquired according to a storage access address sent by the processor core, and after the destination coordinate position is added to a packet header of a data packet, the data packet can reach a memory module to be accessed through the routing unit under the guidance of a destination coordinate. The method can overcome the defects that an existing many-core processor storage system is fixed in address space and does not support ping-pong operation, and memory modules cannot be flexibly combined.

Description

technical field [0001] The invention relates to a storage structure of a many-core processor, in particular to an embedded distributed shared storage structure in which multiple memory modules are integrated inside the many-core processor and parallel access exists among the memory modules. Background technique [0002] Many-core processor memory architecture has become an important factor limiting the improvement of the overall performance of the processor. With the rapid development of integrated circuit design and manufacturing technology, the performance of processor functional components continues to improve, and the powerful computing power brought by the integration of multiple processor cores in a single chip has been growing exponentially according to Moore's law. Far greater than the growth rate of storage bandwidth, the gap between computing speed and memory access speed is getting bigger and bigger. Moreover, as the number of integrated processor cores of many-c...

AI Technical Summary

Problems solved by technology

[0004] In a shared memory system, multiple processor cores access the same memory through an on-chip bus, also known as a symmetric multiprocessor structure, which is characterized in that there is only one main memory in the system, and the main memory is for each processor core It is a completely symmetrical relationship, that is to say, it takes the same time for each processor to access the main memory. The internal data synchronization cost of the storage structure is small, and the storage unit management is simple, but due to the limitations of factors such as transmission delay and memory access bandwidth , the memory access time is relatively long

This centralized shared storage is currently a popular processor storage structure, but its disadvantage is that the scalability of the system is not strong, and the processor can only integrate dozens of cores at most.

On the one hand, the corresponding storage space of each memory module in the processor is fixed. When the application needs to read multiple different data in parallel from this storage space at the same time, since the memory modules only support serial access one by one, the data access time will increase. , the performance of the processor is reduced; on the other hand, the processor integrates many processor cores and memory modules, and the processor cores and memory modules can be divided into multiple groups, and each group is responsible for different tasks. If the processor is a fixed storage structure, disturbed by address space ranges, can greatly affect the compilation and correct execution of multiple tasks

[0017] (2) The storage structure of the current many-core processor cannot effectively support the ping-pong operation in common digital signal processing algorithms

Such ping-pong operations can only be realized in dedicated processing circuits, therefore, the current memory structure affects the further improvement of processor energy efficiency

[0018] (3) The many-core processor integrates multiple memory modules to form a distributed shared storage system. During the data access process of many processor cores, if the address space mapping between the processor core and the memory module is inappropriate, such as the distance is long, there are Parallel access blocking will directly lead to reduced processor performance and increased power consumption

[0019] To sum up, the current many-core processor storage system has the disadvantages of fixed address space, no support for ping-pong operations, and inability to flexibly combine memory modules.

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