Semiconductor device and preparation method thereof

A semiconductor and device technology, applied in the field of semiconductor devices and their preparation, can solve problems such as reducing gate resistance, affecting device frequency characteristics, increasing gate parasitic capacitance, etc., to reduce gate resistance, increase cross-sectional area, and reduce parasitic The effect of capacitance

Pending Publication Date: 2022-05-31
DYNAX SEMICON
0 Cites 0 Cited by

AI-Extracted Technical Summary

Problems solved by technology

However, the design of the shape (physical parameters) of the T-shaped gate structure is different, and the impact on the quality of the gate is also obvious. For example, the gate cap of...
View more

Method used

In summary, in the semiconductor device provided by the embodiment of the present invention, at least two dielectric layers are provided on the side away from the substrate of the multilayer semiconductor layer, and gate trenches are formed in the dielectric layer, and the gate is at least filled in the gate In the pole trench, since the vertical projection of the second sub-trench in the second dielectric layer on the substrate is larger than the vertical projection of the first sub-trench in the first dielectric layer on the substrate, the second gate division The vertical projection of the first grid section on the substrate is larger than the vertical projection of the first grid section on the substrate, and the vertical projection of the third grid section on the substrate covers the vertical projection of the second grid section on the substrate. Therefore, the gate in the semiconductor device provided by the embodiment of the present invention is a multi-step T-shaped gate, that is, the gate has at least two gate caps. Compared with the existing T-shaped gate, the technical solution of the embodiment of the present invention increases the number of gate caps by increasing the number of dielectric layers, which can not only increase the cross-sectional area of ​​the gate, but also further reduce the gate resistance. The electric field distribution at the edge of the gate is improved uniformly and step by step, and the thickness of the dielectric layer between the gate and the two-dimensional electron gas (2DEG) can also be increased to reduce the parasitic capacitance of the gate.
Referring to Fig. 1, the present embodiment is by arranging two layers of dielectric layers, and the vertical projection of the second sub-groove 42 in the second dielectric layer 32 on the substrate 10 is larger than the first sub-groove 42 in the first dielectric layer 31 The vertical projection of the sub-trench 41 on the substrate 10, so that the vertical projection of the second grid subsection 52 on the substrate 10 is larger than the vertical projection of the first grid subsection 51 on the substrate 10, further , since the vertical projection of the third grid subsection 53 on the substrate 10 is larger than the vertical projection of the second grid subsection 52 on the substrate 10, a multi-step T-shaped grid can be formed, further increasing the size of the grid. The cross-sectional area reduces the resistance of the gate. Moreover, since the second dielectric layer 32 is added, the thickness of the dielectric layer between the gate and the two-dimensional electron gas (2DEG) is increased, and the parasitic capacitance of the gate is reduced.
The preparation method of the semiconductor device provided by the embodiment of the present invention, by preparing at least two layers of dielectric layers on the side away from the substrate of the multilayer semiconductor layer, and forming a gate trench in the dielectric layer, the gate is at least filled in In the gate trench, since the vertical projection of the second sub-trench in the second dielectric layer on the substrate is larger than the vertical projection of the first sub-trench in the first dielectric layer on the substrate, the second gate The vertical projection of the division on the substrate is larger than the vertical projection of the first grid division on the substrate, and the vertical projection of the third grid division on the substrate covers the vertical projection of the second grid division on the substrate. Vertical projection, therefore, the gate in the semiconductor device provided by the embodiment of the present invention is a multi-step T-shaped gate, that is, the gate has at least two gate caps. Compared with the existing T-shaped gate, the technical solution of the emb...
View more

Abstract

The embodiment of the invention discloses a semiconductor device and a preparation method thereof, the semiconductor device comprises a substrate, a multi-layer semiconductor layer, a dielectric layer, a grid electrode, a source electrode and a drain electrode, the dielectric layer at least comprises a first dielectric layer close to the substrate and a second dielectric layer far away from the substrate; a gate trench is formed in the dielectric layer, the gate trench at least comprises a first sub-trench penetrating through the first dielectric layer and a second sub-trench penetrating through the second dielectric layer, and the vertical projection of the second sub-trench on the substrate covers the vertical projection of the first sub-trench on the substrate; the grid electrode at least comprises a first grid electrode part, a second grid electrode part and a third grid electrode part which are connected with one another and arranged in a laminated mode, the first grid electrode part fills the first sub-groove, the second grid electrode part fills the second sub-groove, and the vertical projection of the third grid electrode part on the substrate covers the vertical projection of the second grid electrode part on the substrate. The grid electrode of the semiconductor device has low resistance and low parasitic capacitance at the same time, and has good high-frequency characteristics.

Application Domain

Semiconductor/solid-state device manufacturingSemiconductor devices

Technology Topic

PhysicsParasitic capacitor +6

Image

  • Semiconductor device and preparation method thereof
  • Semiconductor device and preparation method thereof
  • Semiconductor device and preparation method thereof

Examples

  • Experimental program(1)

Example Embodiment

The fabrication process of the semiconductor device shown in FIG. 1 is illustrated as an example. Referring to FIG. 8 and FIG. 9 , the preparation method may specifically include the following steps:
[0089] S11, providing a substrate.
[0090] S12, preparing a multilayer semiconductor layer on one side of the substrate.
[0091] Please refer to the description of the above-mentioned semiconductor device embodiments for the structure of the substrate and the multi-layer semiconductor layer, which will not be repeated here.
[0102] Specifically, the vertical projection of the second sub-trench on the substrate covers the vertical projection of the first sub-trench on the substrate.
[0093] Exemplarily, referring to FIG. 9, the formation process of the gate trench may be to prepare a first dielectric layer first,
[0102] Specifically, the vertical projection of the second sub-trench on the substrate covers the vertical projection of the first sub-trench on the substrate.
[0095] The method for preparing a semiconductor device provided by the embodiment of the present invention, by placing the multilayer semiconductor layer on the side away from the substrate

PUM

no PUM

Description & Claims & Application Information

We can also present the details of the Description, Claims and Application information to help users get a comprehensive understanding of the technical details of the patent, such as background art, summary of invention, brief description of drawings, description of embodiments, and other original content. On the other hand, users can also determine the specific scope of protection of the technology through the list of claims; as well as understand the changes in the life cycle of the technology with the presentation of the patent timeline. Login to view more.

Similar technology patents

Drip-proof battery gel-injection equipment

ActiveCN105870396Agood effectIncreased cross-sectional area
Owner:ZHEJIANG YUNBANG BATTERY CO LTD

Drill rig capable of standing stably

InactiveCN107299823AIncreased cross-sectional areaImprove efficiency
Owner:薛帅龙

Mold and method for preparing high-temperature compressive strength test sample of resin sand

PendingCN114136748AIncreased cross-sectional areaImprove stability
Owner:HUAZHONG UNIV OF SCI & TECH

Coil and electronic equipment

ActiveCN108922744AIncreased cross-sectional arealower resistance
Owner:SHANGHAI AMPHENOL AIRWAVE COMM ELECTRONICS

Anti-loosening fastening nut and gasket assembly

PendingCN112268055AIncreased cross-sectional areaImprove fastness
Owner:徐勤

Classification and recommendation of technical efficacy words

  • Increased cross-sectional area

Air-guiding grating, air inlet panel and air conditioner

ActiveCN106766055AIncreased cross-sectional areaBeautiful appearance
Owner:GREE ELECTRIC APPLIANCES INC OF ZHUHAI

Dynamic response characteristic test method for air propeller electric propulsion system

ActiveCN106813891AIncreased cross-sectional areaGood flow field quality
Owner:CHINA ACAD OF AEROSPACE AERODYNAMICS

Coil and electronic equipment

ActiveCN108922744AIncreased cross-sectional arealower resistance
Owner:SHANGHAI AMPHENOL AIRWAVE COMM ELECTRONICS

Drill rig capable of standing stably

InactiveCN107299823AIncreased cross-sectional areaImprove efficiency
Owner:薛帅龙
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products