Semiconductor device and preparation method thereof

A semiconductor and device technology, applied in the field of semiconductor devices and their preparation, can solve problems such as reducing gate resistance, affecting device frequency characteristics, increasing gate parasitic capacitance, etc., to reduce gate resistance, increase cross-sectional area, and reduce parasitic The effect of capacitance

Pending Publication Date: 2022-05-31
DYNAX SEMICON
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Problems solved by technology

However, the design of the shape (physical parameters) of the T-shaped gate structure is different, and the impact on the quality of the gate is also obvious. For example, the gate cap of

Method used

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  • Semiconductor device and preparation method thereof
  • Semiconductor device and preparation method thereof
  • Semiconductor device and preparation method thereof

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Example Embodiment

The fabrication process of the semiconductor device shown in FIG. 1 is illustrated as an example. Referring to FIG. 8 and FIG. 9 , the preparation method may specifically include the following steps:

[0089] S11, providing a substrate.

[0090] S12, preparing a multilayer semiconductor layer on one side of the substrate.

[0091] Please refer to the description of the above-mentioned semiconductor device embodiments for the structure of the substrate and the multi-layer semiconductor layer, which will not be repeated here.

[0102] Specifically, the vertical projection of the second sub-trench on the substrate covers the vertical projection of the first sub-trench on the substrate.

[0093] Exemplarily, referring to FIG. 9, the formation process of the gate trench may be to prepare a first dielectric layer first,

[0102] Specifically, the vertical projection of the second sub-trench on the substrate covers the vertical projection of the first sub-trench on the substrate.

[0095...

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Abstract

The embodiment of the invention discloses a semiconductor device and a preparation method thereof, the semiconductor device comprises a substrate, a multi-layer semiconductor layer, a dielectric layer, a grid electrode, a source electrode and a drain electrode, the dielectric layer at least comprises a first dielectric layer close to the substrate and a second dielectric layer far away from the substrate; a gate trench is formed in the dielectric layer, the gate trench at least comprises a first sub-trench penetrating through the first dielectric layer and a second sub-trench penetrating through the second dielectric layer, and the vertical projection of the second sub-trench on the substrate covers the vertical projection of the first sub-trench on the substrate; the grid electrode at least comprises a first grid electrode part, a second grid electrode part and a third grid electrode part which are connected with one another and arranged in a laminated mode, the first grid electrode part fills the first sub-groove, the second grid electrode part fills the second sub-groove, and the vertical projection of the third grid electrode part on the substrate covers the vertical projection of the second grid electrode part on the substrate. The grid electrode of the semiconductor device has low resistance and low parasitic capacitance at the same time, and has good high-frequency characteristics.

Description

technical field [0001] Embodiments of the present invention relate to the technical field of semiconductors, and in particular to a semiconductor device and a manufacturing method thereof. Background technique [0002] Gallium Nitride (GaN), a semiconductor material, has become a current research hotspot due to its characteristics of large band gap, high electron saturation drift velocity, high breakdown field strength, and good thermal conductivity. In terms of electronic devices, gallium nitride materials are more suitable for manufacturing high-temperature, high-frequency, high-voltage and high-power devices than silicon and gallium arsenide, so gallium nitride-based electronic devices have good application prospects. [0003] In the prior art, the gate structure of GaN devices mainly has a T-shaped gate structure process, and the T-shaped gate structure can effectively improve the distribution of the gate edge and suppress the leakage of the gate edge. However, the desi...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L29/423H01L29/778H01L21/335
CPCH01L29/0603H01L29/42316H01L29/778H01L29/66462
Inventor 赵树峰
Owner DYNAX SEMICON
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