Semiconductor device and preparation method thereof

However, the design of the shape (physical parameters) of the T-shaped gate structure is different, and the impact on the quality of the gate is also obvious. For example, the gate cap of...

In summary, in the semiconductor device provided by the embodiment of the present invention, at least two dielectric layers are provided on the side away from the substrate of the multilayer semiconductor layer, and gate trenches are formed in the dielectric layer, and the gate is at least filled in the gate In the pole trench, since the vertical projection of the second sub-trench in the second dielectric layer on the substrate is larger than the vertical projection of the first sub-trench in the first dielectric layer on the substrate, the second gate division The vertical projection of the first grid section on the substrate is larger than the vertical projection of the first grid section on the substrate, and the vertical projection of the third grid section on the substrate covers the vertical projection of the second grid section on the substrate. Therefore, the gate in the semiconductor device provided by the embodiment of the present invention is a multi-step T-shaped gate, that is, the gate has at least two gate caps. Compared with the existing T-shaped gate, the technical solution of the embodiment of the present invention increases the number of gate caps by increasing the number of dielectric layers, which can not only increase the cross-sectional area of ​​the gate, but also further reduce the gate resistance. The electric field distribution at the edge of the gate is improved uniformly and step by step, and the thickness of the dielectric layer between the gate and the two-dimensional electron gas (2DEG) can also be increased to reduce the parasitic capacitance of the gate.

Referring to Fig. 1, the present embodiment is by arranging two layers of dielectric layers, and the vertical projection of the second sub-groove 42 in the second dielectric layer 32 on the substrate 10 is larger than the first sub-groove 42 in the first dielectric layer 31 The vertical projection of the sub-trench 41 on the substrate 10, so that the vertical projection of the second grid subsection 52 on the substrate 10 is larger than the vertical projection of the first grid subsection 51 on the substrate 10, further , since the vertical projection of the third grid subsection 53 on the substrate 10 is larger than the vertical projection of the second grid subsection 52 on the substrate 10, a multi-step T-shaped grid can be formed, further increasing the size of the grid. The cross-sectional area reduces the resistance of the gate. Moreover, since the second dielectric layer 32 is added, the thickness of the dielectric layer between the gate and the two-dimensional electron gas (2DEG) is increased, and the parasitic capacitance of the gate is reduced.

The preparation method of the semiconductor device provided by the embodiment of the present invention, by preparing at least two layers of dielectric layers on the side away from the substrate of the multilayer semiconductor layer, and forming a gate trench in the dielectric layer, the gate is at least filled in In the gate trench, since the vertical projection of the second sub-trench in the second dielectric layer on the substrate is larger than the vertical projection of the first sub-trench in the first dielectric layer on the substrate, the second gate The vertical projection of the division on the substrate is larger than the vertical projection of the first grid division on the substrate, and the vertical projection of the third grid division on the substrate covers the vertical projection of the second grid division on the substrate. Vertical projection, therefore, the gate in the semiconductor device provided by the embodiment of the present invention is a multi-step T-shaped gate, that is, the gate has at least two gate caps. Compared with the existing T-shaped gate, the technical solution of the emb...