Pipelined-SAR ADC and method for eliminating influence of reference voltage fluctuation
A reference voltage and voltage amplifier technology, applied in electrical components, electrical signal transmission systems, physical parameter compensation/prevention, etc., can solve the problems of ADC linearity and accuracy deterioration, and achieve chip area saving, high linearity and accuracy Effect
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0042] The invention designs a Pipelined-SAR ADC that eliminates the influence of reference voltage fluctuations. The Pipelined-SAR ADC is innovative on the traditional pipeline successive approximation register type analog-to-digital converter. The special design of the capacitor array and the reference voltage connection method solves the problem of "deterioration of ADC linearity and accuracy due to fluctuations in the reference voltage related to the input signal", which ultimately saves the chip area and enables the Pipelined-SAR ADC to achieve High linearity and precision, especially the following setting methods: including the first group of reference voltage Vref1, the second group of reference voltage Vref2, the sample and hold circuit, the first stage SAR ADC, the second stage SAR ADC, digital logic, switch S3 and the residual voltage amplifier, the first set of reference voltages Vref1 is connected to the high-stage capacitor array side on the first-stage CDAC of t...
Embodiment 2
[0044] This embodiment is further optimized on the basis of the above-mentioned embodiment, and the same parts as the above-mentioned technical solutions will not be repeated here, and further to better realize a Pipelined-SAR that eliminates the influence of reference voltage fluctuations described in the present invention The ADC, in particular, adopts the following setting method: the first group of reference voltages Vref1 and the second group of reference voltages Vref2 are connected to the same lead-in terminal of the selection switch side of the high-stage capacitor array through switch S2 through switch S1, and the selection The switch is respectively connected to the sample-hold circuit and the ground level through the other two lead-in terminals, the control terminal of the selection switch is connected to the first-stage CDAC capacitance control signal output by the digital logic, and the lead-out terminal of the selection switch is connected to the corresponding T...
Embodiment 3
[0046] This embodiment is further optimized on the basis of any of the above-mentioned embodiments, and the same parts as the above-mentioned technical solutions will not be repeated here. Further, in order to better realize the Pipelined method of the present invention that eliminates the influence of reference voltage fluctuations -SAR ADC, in particular, the following setting method is adopted: the sample-and-hold circuit is controlled by the control signal Clk_samp generated by digital logic.
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More - R&D
- Intellectual Property
- Life Sciences
- Materials
- Tech Scout
- Unparalleled Data Quality
- Higher Quality Content
- 60% Fewer Hallucinations
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com



