Method of realizing router chip of group exchange network with FPGA device

A technology for switching networks and devices, applied in the direction of logic circuits using specific components, logic circuits using basic logic circuit components, electrical components, etc. The problem of high development cost is easy to set up and expand, the communication bandwidth is improved, and the communication protocol is simplified.

Inactive Publication Date: 2004-06-23
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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Problems solved by technology

[0004] Traditional routing chip design is realized by application-specific integrated circuit (ASIC) devices. Although ASIC devices can guarantee good performance through careful design and advanced technology, due to high development costs, long development cycles, and high production and testing costs, etc., When the chip does not form batches, it does not have a high performance-price ratio; in addition, once the ASIC device is designed and finalized, its logic structure and performance cannot be changed, so new routing methods and logic design ideas cannot be applied in time

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  • Method of realizing router chip of group exchange network with FPGA device
  • Method of realizing router chip of group exchange network with FPGA device
  • Method of realizing router chip of group exchange network with FPGA device

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Embodiment Construction

[0019] Compared with ASIC devices, FPGA devices have the advantages of field programming. With the continuous improvement of production technology, the integration and working speed of FPGA devices have been greatly improved. The logic resources provided inside them, such as digital clock managers , block memory, multiplexer, double-rate flip-flop, etc., can fully meet the requirements of routing chips for logic resources and clock frequency. Using FPGA devices to realize routing chips has the advantages of short design cycle, easy design improvement, and high performance-price ratio. Mature logic implemented with FPGA can also be easily converted into ASIC.

[0020] The present invention will be described in detail below in conjunction with the accompanying drawings.

[0021] Such as figure 2 As shown, the method realizes a routing chip with 8 duplex ports, and the unidirectional transmission bandwidth of each port reaches 4Gbit / S. A scalable cluster switching network can...

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Abstract

The method of realizing router chip of group exchange network with FPGA device includes the following steps: setting inside chip symmetrical I / O ports via utilizing the gate array resource in FPGA; setting inside chip symmetrical crossed logic switches; dispatching the data passages from the input ports to the output ports with arbitration logic; and completing the data exchange task among multiple ports. The kernel of the present invention is universal crossed switches, and the group communication system with the digital exchange chip is easy to constitute and easy to expand. The present invention may be used in various network topology. In addition, the present invention can simplify effectively the communication protocol and this makes it possible for the corresponding exchange equipment to realize safe and efficient communication among group nodes. The present invention makes best use of the resource superiority of FPGA and speed superiority of serial-parallel conversion interface device.

Description

technical field [0001] The invention relates to a method for implementing a cluster interconnection network routing chip by using an FPGA device. Background technique [0002] From the perspective of hardware structure, the cluster system is a computer system that connects several high-performance processing nodes through a high-speed switching network and can realize high-speed parallel processing. The performance of a single node in the cluster system is getting higher and higher, requiring that the performance of the switching network must match the performance of the node, otherwise it will become the bottleneck of the entire system. The routing chip is the core component of the cluster switching network, and the performance of the routing chip has a decisive impact on the performance of the cluster switching network. It is of great significance to design and construct a scalable, high-performance cluster switching network routing chip. A scalable switching network see...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/173H04Q3/52
Inventor 安学军高文学吴冬冬张佩珩刘新春
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI
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