Operation method of non-volatile memory unit array

Abstract

The invention provides a nonvolatile storage cell array operating method, applied to operating NAND storage cell array, where each storage cell has a charge immersing layer. When operating the array, it uses F-N tunneling effect to erase the whole storage cell array and uses thermal electric hole-injecting effect to code a single bit in a single storage cell. With the F-N tunneling effect, its electron injecting efficiency is high, thus able to reduce the current of the storage cell when erasing and at the same time enhance operating speed. Moreover, the current consumption is low, able to effectively reduce the power loss of the whole chip.

Description

technical field [0001] The present invention relates to a method for operating a non-volatile memory cell array (Non-Volatile Memory Array), and in particular to an electrically erasable and programmable The operation method of the read-only memory (Electrically Erasable Programmable Read Only Memory, EEPROM) array. Background technique [0002] The electrically erasable and programmable read-only memory in the non-volatile memory has the advantage of being able to store, read, and erase data multiple times, and the stored data will not disappear after power off. Therefore, it has become a memory device widely used in personal computers and electronic equipment. [0003] A typical electrically erasable and programmable read-only memory uses doped polysilicon to make a floating gate (Floating Gate) and a control gate (Control Gate). When the memory is programmed, the electrons injected into the floating gate are uniformly distributed throughout the polysilicon floating gate...

AI Technical Summary

Problems solved by technology

However, when the used voltage increases, the reliability of electronic devices will be reduced due to the high leakage current and low programming efficiency caused by the punch-through effect, especially when the memory device The smaller the size of the device, the more serious the high leakage current and low programming efficiency caused by the punch-through effect will be, which will limit the degree of device size reduction.

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