CMOS comparator

Abstract

The CMOS comparator has feedback offset regulating circuit comprising switching capacitor filter and voltage regulating circuit, output latch with output connected to the input of the switching capacitor, the output of the switching capacitor filter connected to the input of the voltage regulating circuit, the output of voltage regulating circuit connected to one end of the comparator offset correcting capacitor C3, the other end of C3 connected to the non-inversion input of the first amplifier, and the capacitor C4 as the capacitor of C3 with one end connected to the inversion input of the first amplifier and the other end grounded. The switching capacitor filter consists of the first branch and the second branch, the first branch consists of two transmission gates, the second branch consists of one inverter and two other transmission gates, and the inverter has its input connected to the output of the output latch.

Description

technical field [0001] The invention relates to a comparator circuit suitable for successive approximation analog-to-digital converters, pipeline structure analog converters and other high-precision comparators, in particular to a complementary metal-oxide-semiconductor comparator. Background technique [0002] Speed ​​and precision are two of the most important characteristics of analog circuits, especially in high-speed and high-precision analog-to-digital converters (ADCs). However, the speed and accuracy of the ADC circuit are usually determined by the accuracy and speed of the comparator, because the comparator input offset and delay directly affect the accuracy and speed of the analog-to-digital converter circuit. Due to process drift, the mismatch of circuit elements in the comparator makes the comparator input offset voltage usually about 50mV. Therefore, in order to meet the high-precision analog-to-digital converter (ADC) design, it is ...

AI Technical Summary

Problems solved by technology

Although input offset storage and output offset storage can greatly reduce the input offset voltage of the comparator, these two offset cancellation techniques need to add an offset storage capacitor to the signal transmission path, which reduces the speed of the comparator, and it cannot eliminate the transistor switch. The effect of channel charge injection and clock feedthrough on the input offset voltage caused by

For on-chip resistor laser trimming, the calibration process is only performed once during chip manufacturing, which requires the circuit to have time and temperature stability, and requires additional calibration procedures, increasing costs

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