Method of reducing dislocation-induced leakage in a strained-layer field-effect transistor

Abstract

A structure and method of fabricating a semiconductor field-effect transistor (MOSFET) such as a strained Si n-MOSFET where dislocation or crystal defects spanning from source to drain is partially occupied by heavy p-type dopants. Preferably, the strained-layer n-MOSFET includes a Si, SiGe or SiGeC multi-layer structure having, in the region between source and drain, impurity atoms that preferentially occupy the dislocation sites so as to prevent shorting of source and drain via dopant diffusion along the dislocation. Advantageously, devices formed as a result of the invention are immune to dislocation-related failures, and therefore are more robust to processing and material variations. The invention thus relaxes the requirement for reducing the threading dislocation density in SiGe buffers, since the devices will be operable despite the presence of a finite number of dislocations.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to semiconductors and transistors and more particularly to Si / SiGe strained-layer field-effect transistors. [0003] 2. Description of the Prior Art [0004] Semiconductor Si / SiGe strained-layer MOSFETs fabricated using strained Si have potential for improved performance due to higher carrier mobility in the strained Si layer. The strain in the Si is typically achieved by first forming a relaxed SiGe layer, and then epitaxially growing the Si layer on top. Since the SiGe has a larger lattice constant than Si, the Si will be under tensile strain. The underlying relaxed SiGe layer can be formed in numerous ways, but is typically formed by growing a graded-Ge-content SiGe layer on a Si substrate, followed by a thick constant-composition SiGe layer. The SiGe relaxes by misfit dislocation formation near the original growth interface, with a fairly high density (on the order of about 106 cm−2-108...

AI Technical Summary

Benefits of technology

[0014] Advantageously, the device and fabricating method of the invention relaxes the requirement for reducing the threading d

Problems solved by technology

The threading and misfit dislocations can lead to device failure in a short-channel MOSFET fabricated on these layers particularly if the dislocation extends continuously from the source implant region to the drain implant region.

In this case, the dopants from the source and drain can segregate along the dislocation, causing a direct “pipe” from source to drain, resulting in device leakage.

Since larger atoms can preferentially occupy dislocation sites, n-MOSFETs are more likely to suffer from dislocation-related failures of the type described above.

The data shows that the leakage is seen to occur directly from source to drain (and not from source to body or drain to body, Ib), resulting in poor turn off behavior and high leakage 55 in the subthreshold region (Vgs<0).

Both of these methods have been successful in reducing dislocation-induced leakage, but it is very difficult to comp

Images