Inspection apparatus for inspecting patterns of a substrate

Abstract

A pattern inspection apparatus has a setting unit of a plurality of cell areas A and B of different cell comparison pitches and inspects the plurality of cell areas of the different cell comparison pitches in accordance with settings of the setting unit. As information to read out image data for an inspection image and a reference image from an image memory, in addition to position information of a defective image, identification information showing either a cell comparison or a die comparison and relative position information of the reference image can be set. The apparatus also has a unit for setting a plurality of inspection threshold values every inspection area and inspects a plurality of inspection areas by the plurality of inspection threshold values.

Description

BACKGROUND OF THE INVENTION [0001] The invention relates to a pattern inspection apparatus of a substrate having a fine circuit pattern like a semiconductor device, liquid crystal, or the like and, more particularly, to a pattern inspection apparatus which is suitable when it is applied to a pattern inspection on a wafer during a semiconductor device manufacturing step. [0002] An inspection of a semiconductor wafer will be described as an example. A semiconductor device is manufactured by repeating a step of transferring a pattern formed on a photomask onto the semiconductor wafer by a lithography process and an etching process. In the manufacturing step of the semiconductor device, whether or not the lithography process, the etching process, and the like have correctly been executed, occurrence of a foreign matter, or the like largely influences on a yield of the semiconductor device. Therefore, a method of inspecting the pattern on the semiconductor wafer in order to early or prel...

AI Technical Summary

Benefits of technology

[0052] According to the invention, the existence of an uninspectable area at the time of the die comparison can be avoided. Also in the case of extracting the defective images in the different cell pitch areas, the inspection can be performed in one inspection. Further, since the mixture inspection of the cell comparison and the die comparison can be performed, the inspecting efficiency is improved.

[0053] According to the invention, since a plurality of inspection areas can be inspected in a lump by different inspection threshold values, the throughput can be improved.

Problems solved by technology

In the case where the semiconductor wafer in the manufacturing step is inspected by such optical inspection systems as mentioned above, a residual or a defect of the pattern having a silicon oxide film or a photosensitive photoresist material through which light is transmitted on the surface cannot be detected.

Further, a defect occurring in a stairway bottom portion of a wiring pattern cannot be detected.

In the case of the electron beam of a large current and low acceleration, it is difficult to obtain an image of high resolution due to a space-charge effect.

However, in such a type of detection apparatus, since the light emission by phosphor is detected, frequency response characteristics are bad and it is improper to form the electron beam image at a high speed.

An ease of use is bad in both of management and creation of the recipe.

Further, since a plurality of inspection steps are executed every cell, there is such a drawback that the inspecting time becomes long.

However, for example, if a defect is detected in the first chip shown in FIG. 16A, since the one-chip precedent image does not exist and there is no reference image, defect analysis of the first chip is impossible.

Therefore, the reference image includes a larger amount of positional deviation error and a larger amount of error of image concentration or the like and cannot be used as a reference image.

Therefore, even if the defect is detected in the (n+1)th chip in the wafer edge portion, the defect analysis is impossible.

However, since columns of the (n+1)th chip and the nth chip of the chip layouts are different in FIG. 16B, when compared with the relation between the adjacent chips of the same column (for example, the nth chip and the (n−1)th chip), the conditions upon obtaining the images are different and the reference image includes a larger amount of positional deviation error and the like.

Although there is no problem if such an error lies within a correction range of an image processing function, if not, even in the case of FIG. 16B, there is also a possibility that the image of the nth chip cannot be used as a reference image of the (n+1)th chip.

As mentioned above, if the defect is detected in the chip in the semiconductor wafer edge portion and becomes a defect analysis target, since the one-chip precedent image does not exist, the reference image does not exist and a situation that the defect analysis cannot be performed occurs.

However, hitherto, a plurality of cell pitches in the case of the cell comparison cannot be designated.

As mentioned above, according to the related art, since it is necessary to set the cell pitch for each cell pitch area and execute the inspection again, efficiency is very low.

Further, in the die comparison and the cell comparison, since definitions of the reference images which are necessary for the inspection images are different, the cell comparison and the die comparison cannot be mixedly executed.

There is such a drawback that the inspecting time becomes long because a plurality of inspecting steps are repeated.

Further, since a plurality of recipes are needed for one inspection, ease of use is bad in both of the management of the inspection recipes and the creation of the recipes.

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