Array-Processed Stacked Semiconductor Packages

Abstract

One embodiment of the invention is a semiconductor system (1400) of arrays (1401, 1402, etc.) of packaged devices. Each array includes a sheet-like substrate (1411, 1412, etc.) made of insulating material integral with conductive horizontal lines and vertical vias, and terminals on the surfaces. Semiconductor components, which may include more than one active or passive chips, or chips of different sizes, are attached to the substrate; the electrical connections may include flip-chip, wire bond, or combination techniques. Encapsulation compound (1412, 1422, etc.), which adheres to the substrate, embeds the connected components. Metal posts (1431, 1432, etc.) traverse the encapsulation compound vertically, connecting the substrate vias with pads on the encapsulation surface. The pads are covered with solder bodies used to connect to the next-level device array so that a 3-dimensional system of packaged devices is formed.

Description

FIELD OF THE INVENTION[0001]The present invention is related in general to the field of semiconductor devices and processes, and more specifically to array-processed stacked semiconductor packages creating 3-dimensionally interconnected chips.DESCRIPTION OF THE RELATED ART[0002]The long-term trend in semiconductor technology to double the functional complexity of its products every 18 months (Moore's “law”) has several implicit consequences. First, the higher product complexity should largely be achieved by shrinking the feature sizes of the chip components while holding the package dimensions constant; preferably, even the packages should shrink. Second, the increased functional complexity should be paralleled by an equivalent increase in reliability of the product. Third, the cost per functional unit should drop with each generation of complexity so that the cost of the product with its doubled functionality would increase only slightly.[0003]As for the challenges in semiconductor...

AI Technical Summary

Benefits of technology

[0010]The array is bonded to the next array using solder attachment on the metallization (alternatively, thermo-compression bonding may be used). The reflow of multiple stacked packages occurs at one time for the whole array. To enhan

Problems solved by technology

First, the higher product complexity should largely be achieved by shrinking the feature sizes of the chip components while holding the package dimensions constant; preferably, even the packages should shrink.

Second, the increased functional complexity should be paralleled by an equivalent increase in reliability of the product.

Third, the cost per functional unit should drop wit

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