Method for measuring interface traps in thin gate oxide MOSFETs

Abstract

A method for measuring interface traps in a MOSFET, comprising measuring charge pumping current of a pulse wave form for various frequencies over a predetermined frequency range, creating plotted points of the measured charge pumping current versus the predetermined frequency range, determining the total number of interface traps participating in the charge pumping current by calculating the slope of a best fit line through the plotted points.

Description

TECHNICAL FIELD[0001]The present invention relates to interface traps within MOSFETs, and in particular to a method for measuring interface traps in thin gate oxide MOSFETs.BACKGROUND OF THE INVENTION[0002]As is known in the art, semiconductor wafers often contain material interfaces such as between silicon and silicon dioxide. Contaminants and other defects at the oxide silicon interface can cause problems in the manufacture and performance of integrated circuits that are fabricated over that interface. These defects, often referred to as interface traps, are capable of trapping and de-trapping charge carriers. Interface traps can have an adverse effect on device performance, for example, an interface trap can cause discrete switching in the source conductance, band-to-band tunneling (BBT) of hot carriers from the gate-to-drain which can result in gate-induced drain leakage current, drain current fluctuation, voltage drop in the gate area, threshold voltage shift in the MOS transis...

AI Technical Summary

Problems solved by technology

Contaminants and other defects at the oxide silicon interface can cause problems in the manufacture and performance of integrated circuits that are fabricated over that interface.

Interface traps can have an adverse effect on device performance, for example, an interface trap can cause discrete switching in the source conductance, band-to-band tunneling (BBT) of hot carriers from the gate-to-drain which can result in gate-induced drain leakage current, drain current fluctuation, voltage drop in the gate area, threshold voltage shift in the MOS transistors, and the like.

The traditional charge pumping technique for characterizing interface traps fails when tunneling current is comparable to or greater than the charge pumping current, as it is difficult to separate the two currents.

A-priori estimation of the average gate tunneling current (which is a function of the gate voltage waveform) into the bulk or source / drain of the MOSFET during charge pumping leads to inaccuracies due to the exponential dependence of gate tunneling current on the gate voltage.

However, some of the traps will remain “trapped” and recombine with the inversion charge or the accumulation charge coming from the bulk.

There is a substantial current measurement difference between devices, when evaluating an enhanced complementary metal oxide semiconductor (CMOS) as opposed to a MOSFET where they gate dielectric is very thin.

Utilizing a thin gate dielectric, if there is an increase in the voltage beyond inversion, or if the device is taken to deep accumulation, that results in a significant amount of gate current.

However, this gate current is small, when compared to a normal MOSFET operating current, which is the source / drain current.

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