Cobalt capping surface preparation in microelectronics manufacture

Abstract

Cleaning compositions and methods in connection with cobalt-based capping of interconnects in integrated circuit semiconductor devices.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims priority from U.S. App. Ser. No. 60 / 909,654, filed Apr. 2, 2007, entitled Cobalt Capping Surface Preparation in Microelectronics Manufacture.FIELD OF THE INVENTION[0002]The present invention generally relates to the preparation of wafers and conductive surfaces of interconnect features thereof prior to electroless cobalt deposition and to the cleaning of wafers and cobalt capping layers after electroless deposition.BACKGROUND OF THE INVENTION[0003]The demand for semiconductor integrated circuit (IC) devices such as computer chips with high circuit speed and high circuit density requires the downward scaling of feature sizes in ultra-large scale integration (ULSI) and very-large scale integration (VLSI) structures. The trend to smaller device sizes and increased circuit density requires decreasing the dimensions of interconnect features and increasing their density. An interconnect feature is a feature such as a via ...

AI Technical Summary

Benefits of technology

The present invention is about a composition and method for cleaning the surface of a semiconductor integrated circuit device before applying a cobalt-based capping layer. The composition includes a reducing agent, a proton source, a particle suspension agent, and a surfactant, with a pH of less than about 6.0. The invention also includes a composition for cleaning the electrolessly deposited cobalt-based capping layer on an interconnect featuring metallization. The composition includes a reducing agent, a proton source, a surfactant, and a particle suspension agent. The technical effects of the invention include improved cleaning efficiency and better adhesion between the capping layer and the substrate surface, which leads to better performance and reliability of semiconductor devices.

Problems solved by technology

Such diffusion can be detrimental to the device because it can cause electrical leakage in substrates or form an unintended electrical connection between two interconnects resulting in an electrical short.

Moreover, copper diffusion out of an interconnect feature can disrupt electrical flow therethrough.

This migration can damage an adjacent interconnect line, and disrupt electrical flow in the feature from which the metal migrates.

During any of the device manufacturing stages, the possibility of non-uniform, as opposed to planar, surfaces (i.e., copper interconnect surface roughness and variations in the wafer surface) arises.

Additionally, processing steps, such as CMP, may leave residues on the surfaces of the both the dielectric material and the copper interconnect.

Further, CMP may result in roughness of the copper surface and may leave a layer of copper oxides on the metallization layer or even on the wafer surface.

These defects related to both surface non-uniformity and residues may cause, during electroless deposition of the cap, cobalt particle nucleation and growth on both the cobalt cap and on the wafer surface.

Moreover, surface roughness can entrap contaminants during wet processing, cause defects and voids thereby promoting electromigration failure, affect the signal propagation across the circuitry, and promote nodular, dendritic growth of the electroless deposit at the interface between the cobalt cap and copper interconnect.

These defects can significantly reduce selectivity of the capping layer, increase current leakage, and in extreme cases even result in electrical shorts.

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